| Integrated Circuits (ICs) | 2 | Active | The MC74HCT20A is identical in pinout to the LS20. The device inputs are compatible with standard CMOS LSTTL outputs. |
| Buffers, Drivers, Receivers, Transceivers | 2 | Active | |
74HCT244Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver, TTL Level | Buffers, Drivers, Receivers, Transceivers | 1 | Active | The MM74HCT240 and MM74HCT244 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. All three devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT240 is an inverting buffer and the MM74HCT244 is a non-inverting buffer. Each device has two active low enables (1G and 2G), and each enable independently controls 4 buffers. All inputs are protected from damage due to static discharge by diodes to VCCand Ground. |
74HCT245Octal 3-State Non-Inverting Bus Transceiver | Integrated Circuits (ICs) | 1 | Active | The MM74HCT245 3-STATE bi-directional buffer utilizes advanced silicon-gate CMOS technology and is intended for two-way asynchronous communication between data buses. It has high drive current outputs which enable high speed operation even when driving large bus capacitances. This circuit possesses the low power consumption of CMOS circuitry, yet has speeds comparable to low power Schottky TTL circuits. This device is TTL input compatible and can drive up to 15 LS-TTL loads, and all inputs are protected from damage due to static discharge by diodes to VCCand ground. The MM74HCT245 has one active low enable input (G#), and a direction control (DIR). When the DIR input is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from B to A. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. |
| Signal Switches, Multiplexers, Decoders | 3 | Active | |
74HCT2598-Bit Addressable Latch 1-of-8 Decoder | Integrated Circuits (ICs) | 2 | Active | The MC74HCT259A is identical in pinout to the LS259. The device inputs are compatible with standard CMOS and LSTTL outputs. The HCT259A has four modes of operation as shown in the mode selection table. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all nonaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the oneofeight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode all outputs are LOW and unaffected by the address and data inputs. When operating the HCT259A as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. |
| Logic | 1 | Active | |
| Buffers, Drivers, Receivers, Transceivers | 1 | Active | |
| Integrated Circuits (ICs) | 1 | Active | |
| Logic | 3 | Active | |
