72V716232K x 2K TSI, 16 I/O at 2/4/8 or 16Mbps, Rate-Matching, 3.3V | Signal Switches, Multiplexers, Decoders | 3 | Obsolete | A ST-BUS® compatible digital switch controlled by amicroprocessor which can handle from 128 x 128 to 32K x 32K inputs to multiple outputs. |
| Integrated Circuits (ICs) | 2 | Obsolete | |
72V7166016K x 16K TSI, 64 I/O at 2/4/8 or 16Mbps, 3.3V | Signal Switches, Multiplexers, Decoders | 2 | Obsolete | A ST-BUS® compatible digital switch controlled by amicroprocessor which can handle from 128 x 128 to 32K x 32K inputs to multiple outputs. |
| Integrated Circuits (ICs) | 2 | Obsolete | 3.3V 2K X 72 SUPERSYNCII |
| FIFOs Memory | 1 | Obsolete | 3.3V 32K X 72 SUPERSYNCII |
72V7326016K x 16K TSI, 32 I/O at 32Mbps, 3.3V | Logic | 1 | Obsolete | A ST-BUS® compatible digital switch controlled by amicroprocessor which can handle from 128 x 128 to 32K x 32K inputs to multiple outputs. |
| Logic | 2 | Active | |
72V801256 x 9 DualSync FIFO, 3.3V | Logic | 2 | Obsolete | The 72V801is a 256 x 9 dual synchronous FIFO that is functionally equivalent to two 72V201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. |
72V811512 x 9 DualSync FIFO, 3.3V | Integrated Circuits (ICs) | 2 | Obsolete | The 72V811is a 512 x 9 dual synchronous FIFO that is functionally equivalent to two 72V211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. |
72V815512 x 18 DualSync FIFO, 3.3V | Logic | 4 | Obsolete | The 72V815 is a 512 x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V215 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. |
