71V4243.3V 512K x 8 Asynchronous Static RAM Center Power & GND Pinout | Integrated Circuits (ICs) | 29 | Active | The 71V424 3.3V CMOS SRAM is organized as 512K x 8. All bidirectional inputs and outputs of the 71V424 are TTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. |
71V5463.3V 128K x 36 ZBT Synchronous Pipelined SRAM | Memory | 5 | Obsolete | The 71V546 3.3V CMOS SRAM, organized as 128K x 36 bits, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V546 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V5473.3V 128K x 36 ZBT Synchronous Flow-Through SRAM | Memory | 4 | Active | The 71V547 3.3V CMOS SRAM is organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turn-around. The 71V547 contains address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V6323.3V 64K x 32 Synchronous PipeLined Burst SRAM | Memory | 4 | Obsolete | The 71V632 3.3V CMOS SRAM is organized as 64K x 32. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz. The 71V632 SRAM contains write, data, address, and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. |
71V656033.3V 256K X 36 ZBT Synchronous 3.3V I/O Pipelined SRAM | Integrated Circuits (ICs) | 32 | Active | The 71V65603 3.3V CMOS SRAM, organized as 256K X 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65603 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V657033.3V 256K x 36 ZBT Synchronous 3.3V I/O Flow-Through SRAM | Integrated Circuits (ICs) | 27 | Active | The 71V65703 3.3V CMOS SRAM, organized as 256K x 36, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65703 contains address, data-in, and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V658033.3V 512K x 18 ZBT Synchronous 3.3V I/O Pipelined SRAM | Memory | 25 | Active | The 71V65803 3.3V CMOS SRAM, organized as 512K X 18, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65803 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V659033.3V 512K x 18 ZBT Synchronous 3.3V I/O Flow-Through SRAM | Integrated Circuits (ICs) | 15 | Active | The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBT™, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM. |
71V676023.3V 256K x 36 Synchronous 2.5V I/O PipeLined SRAM | Integrated Circuits (ICs) | 13 | Active | The 71V67602 3.3V CMOS SRAM is organized as 256K x 36. The 71V676 SRAM contains write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM. |
71V676033.3V 256K x 36 Synchronous 3.3V I/O PipeLined SRAM | Memory | 25 | Active | The 71V67603 3.3V CMOS SRAM is organized as 256K x 36. The 71V67603 SRAM contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.The order of these three addresses are defined by the internal burst counter and the LBO input pin. |
