The 580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can also be configured to switch automatically if one of the input clocks stops. The part also provides clock detection by reporting when an input clock has stopped. For a clock mux with zero delay and smooth switching, see either the 581-01 or the 581-02.

The ICS581-01 is a glitch free, Phase Locked Loop(PLL) based clock multiplexer (mux) with zero delay frominput to output. It has have four low skew outputswhich can be configured as a single output, three outputs,or four outputs. The ICS581-01 allows user control over themux switching.The ICS581-01 is a member of IDT’sClockBlocksTM family of clock generation, synchronization,and distribution devices. For a non-PLL based clock mux,see the ICS580-01.

The 5962-38294 (7164) SRAM is organized as 8K x 8 and offers a reduced power standby mode. The low-power version also offers a battery backup data retention capability at power supply levels as low as 2V. All inputs and outputs are TTL-compatible and operation is from a single 5V supply, simplifying system designs. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation.

The 5962-86875 (7130/40) is a high-speed 1K x 8 dual-port static RAM designed to be used as a stand-alone 8-bit dual-port RAM or as a "Master" dual-port RAM together with a "Slave" dual-port in 16-bit or more word width systems which would result in full-speed, error-free operation without the need for additional discrete logic. An automatic power-down feature, controlled by Chip Enable (CE) permits the on-chip circuitry of each port to enter a very low standby power mode. The military-grade product complies with MIL-PRF-38535 QML.

The 5962-87531 (IDT 7201) is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.

The 5962-88552 (71256 SRAM) is organized as 32K x 8. This part offers a reduced power standby mode for significant system level power and cooling savings. It also offers a battery backup data retention capability allowing operation off a 2V battery. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.

The 5962-88662 (71256 SRAM) is organized as 32K x 8. This part offers a reduced power standby mode for significant system level power and cooling savings. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.