Renesas Electronics Corporation

The CA5420A is an integrated circuit operational amplifier that combines PMOS transistors and bipolar transistors on a single monolithic chip. It is designed and guaranteed to operate in microprocessor logic systems that use V+ = 5V, V- = GND, since it can operate down to ±1V supplies. It will also be suitable for 3. 3V logic systems. The CA5420A BiMOS operational amplifier features gate-protected PMOS transistors in the input circuit to provide very high input impedance, very low input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for reducing the doubling of leakage current for every +10°C increase in temperature. The CA5420A operates at total supply voltages from 2V to 20V either single or dual supply. This operational amplifier is internally phase compensated to achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of PMOS in the input stage results in common-mode input voltage capability down to 0. 45V below the negative supply terminal, an important attribute for single supply application. The output stage uses a feedback OTA type amplifier that can swing essentially from rail-to-rail. The output driving current of 1. 0mA (Min) is provided by using nonlinear current mirrors. This device has guaranteed specifications for 5V operation over the full military temperature range of -55°C to +125°C. The CA5420A has the same 8 lead pinout used for the industry standard 741.

The CA91C142D (Universe II) is the industry's leading high-performance PCI to VME interconnect. It is fully compliant with the VME64 bus standard, and is tailored to support advanced PCI processors and peripherals. With a zero wait state implementation for write transactions, and the capability to support pre-fetch reads and multi-beat transactions, the Universe II provides high performance utilization of the PCI bus. The Universe II eases development of VMEbus systems by providing direct connection to a local PCI bus. The device is ideally suited for CPU or peripheral boards functioning as both master and slave in the VMEbus system. Bridging is accomplished through a decoupled architecture with independent FIFOs for inbound (VME to PCI), outbound (PCI to VME), and DMA traffic. With this architecture, throughput is maximized without sacrificing bandwidth on either bus. Designing with the Universe II eases the development of VME Single Board Computers (SBCs) and I/O peripherals targeting the military, aerospace, industrial automation and medical markets.

The CA91L8200B (PowerSpan II Dual) is a multi-port PCI bus switch that bridges PCI to the PowerQUICC II (MPC8260), MPC7xx, PowerPC™ 7xx, and PMC-Sierra WinPath™ processors. The integrated, non-transparent PCI-to-PCI bridge in the dual PCI PowerSpan II allows designers to reduce component count and increase overall system performance.

The CA91L8260B (PowerSpan II Single) is a single-port PCI bus switch that bridges PCI to the PowerQUICC II (MPC8260), MPC7xx, PowerPC™ 7xx, and PMC-Sierra WinPathT™ processors.

The CA91L862A (QSpan II) is a PCI-to-Host processor bridge for the Freescale PowerQUICC (MPC860/850/821), the QUICC (MC68360), and the MC68040 processors. The QSpan II operates at speeds up to 50 MHz on the processor bus, with programmable parity and burst/prefetch capability. It provides 32-bit / 33 MHz PCI 2.2 support for embedded processor applications.

CD40105BMS is a low-power first-in-first-out (FIFO) elastic storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A 1 signifies that the position's data is filled and a 0 denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the 0 state and sees a 1 in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to 0. The first and last control flip-flops have buffered outputs. Since all empty locations bubble automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output.

CD4073BMS, CD4081BMS and CD4082BMS AND gates provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.