74AUP2G57Low-power dual PCB configurable multiple function gate | Logic | 3 | Active | The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCCor GND. |
| Integrated Circuits (ICs) | 1 | Active | The 74AUP2G57-Q100 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCCor GND. |
74AUP2G58DPLow-power dual PCB configurable multiple function gate | Logic | 1 | Active | The 74AUP2G58 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCCor GND. |
74AUP2G58GULow-power dual PCB configurable multiple function gate | Gates and Inverters - Multi-Function, Configurable | 1 | Active | The 74AUP2G58 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions AND, OR, NAND, NOR, XOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCCor GND. |
74AUP2G79Low-power dual D-type flip-flop; positive-edge trigger | Flip Flops | 3 | Active | The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. |
74AUP2G79DCLow-power dual D-type flip-flop; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. |
74AUP2G79GNLow-power dual D-type flip-flop; positive-edge trigger | Logic | 1 | Active | The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. |
74AUP2G80Low-power dual D-type flip-flop; positive-edge trigger | Flip Flops | 2 | Active | The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to theQoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. |
| Flip Flops | 1 | Active | The 74AUP2G80-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to theQoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. |
74AUP2G80GSLow-power dual D-type flip-flop; positive-edge trigger | Logic | 1 | Active | The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to theQoutput on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation. |
