HEF40948-stage shift-and-store register | Shift Registers | 5 | Active | The HEF4094B-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
HEF4104Quad low-to-high voltage translator with 3-state outputs | Integrated Circuits (ICs) | 2 | Active | The HEF4104B is a quad low-to-high voltage translator with complementary 3-state outputs (Bn andBn). A LOW on the output enable input (OE) causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Logic | 1 | Active | |
| Logic | 2 | Active | The HEF4520B-Q100 is a dual 4-bit internally synchronous binary counter with two clock inputs (nCP0 and nCP1), buffered outputs from all four bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on either the LOW-to-HIGH transition of nCP0 if nCP1 is HIGH or the HIGH-to-LOW transition of nCP1 if nCP0 is LOW. Either nCP0 or nCP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on nMR resets the counter (nQ0 to nQ3 = LOW) independent of nCP0 and nCP1. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. |
| Logic | 1 | Obsolete | |
HEF4521BT24-stage frequency divider and oscillator | Counters, Dividers | 1 | Active | The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) functions as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when pins VSS1and VDD1are supplied via external resistors. |
| Integrated Circuits (ICs) | 1 | Active | The HEF4521B-Q100 consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (A2 to Y2) functions as: a crystal oscillator, an input buffer for an external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator operates in Low-power mode when pins VSS1and VDD1are supplied via external resistors. |
HEF4528Dual monostable multivibrator | Integrated Circuits (ICs) | 3 | Active | The HEF4528B-Q100 is a dual retriggerable-resetable monostable multivibrator. Each multivibrator has an active LOW input (nA), and active HIGH input (nB), an active LOW clear direct input (nCD), an output (nQ) and its complement (nQ), and two external timing component connecting pins (nCEXT, always connected to ground, and nREXT/CEXT). |
| Multivibrators | 2 | Active | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
