| Logic | 1 | Active | The 74AHC86-Q100; 74AHCT86-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC9541A is an 8-bit buffer/line driver with 3-state outputs and Schmitt trigger inputs. The device features an output enable input (OE) and select input (S). A HIGH onOEcauses the associated outputs to assume a high-impedance OFF-state. A LOW on the select input S causes the buffer/line driver to act as an inverter. |
| Gates and Inverters | 2 | Active | |
| Gates and Inverters | 1 | Active | The 74AHC00-Q100; 74AHCT00-Q100 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC00; 74AHCT00 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Gates and Inverters | 1 | Active | The 74AHC00; 74AHCT00 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC00; 74AHCT00 are quad 2-input NAND gates. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Gates and Inverters | 4 | Active | The 74AHC02-Q100; 74AHCT02-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Integrated Circuits (ICs) | 6 | Active | The 74AHC04-Q100; 74AHCT04-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |