74LVC595APW8-bit serial-in/serial-out or parallel-out shift register; 3-state | Shift Registers | 1 | Active | The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. |
74LVC74Dual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 6 | Active | The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQoutputs. |
74LVC74ABQDual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQoutputs. |
74LVC74ABZDual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQoutputs. |
74LVC74APW-Q100Dual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQoutputs. |
| Integrated Circuits (ICs) | 3 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Active | The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Gates and Inverters | 1 | Active | The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Gates and Inverters | 1 | Active | The 74LVC86A is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Integrated Circuits (ICs) | 1 | Active | The 74LVC86A-Q100 is a quad 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
