| Integrated Circuits (ICs) | 1 | Active | The 74AHC126-Q100; 74AHCT126-Q100 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC126; 74AHCT126 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A LOW on nOE causes the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Gates and Inverters | 1 | Active | The 74AHC132-Q100; 74AHCT132-Q100 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Gates and Inverters | 1 | Active | The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC132; 74AHCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC132-Q100; 74AHCT132-Q100 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC1383-to-8 line decoder/demultiplexer; inverting | Logic | 4 | Active | The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. |
| Logic | 1 | Active | The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. |
74AHC139Dual 2-to-4 line decoder/demultiplexer | Logic | 2 | Active | The 74AHC139; 74AHCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nEis HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
