| Integrated Circuits (ICs) | 1 | Active | The 74HC08-Q100; 74HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Gates and Inverters | 1 | Active | The 74HC08-Q100; 74HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 1 | Active | The 74HC08; 74HCT08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74HC08-Q100; 74HCT08-Q100 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 3 | Active | The 74HC10; 74HCT10 is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HCT107DDual JK flip-flop with reset; negative-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q andQoutputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q andQoutputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HCT109Dual JK flip-flop with set and reset; positive-edge-trigger | Flip Flops | 3 | Active | The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JKflip-flop featuring individual J andKinputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q andQoutputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J andKinputs control the state changes of the flip-flops as described in the mode select function table. The J andKinputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JKdesign allows operation as a D-type flip-flop by connecting the J andKinputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HCT109DDual JK flip-flop with set and reset; positive-edge-trigger | Logic | 1 | Active | The 74HC109; 74HCT109 is a dual positive edge triggered JKflip-flop featuring individual J andKinputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q andQoutputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J andKinputs control the state changes of the flip-flops as described in the mode select function table. The J andKinputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JKdesign allows operation as a D-type flip-flop by connecting the J andKinputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HCT109PWDual JK flip-flop with set and reset; positive-edge-trigger | Flip Flops | 1 | Active | The 74HC109; 74HCT109 is a dual positive edge triggered JKflip-flop featuring individual J andKinputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q andQoutputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J andKinputs control the state changes of the flip-flops as described in the mode select function table. The J andKinputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JKdesign allows operation as a D-type flip-flop by connecting the J andKinputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
