| Logic | 1 | Obsolete | |
| Gates and Inverters | 1 | Active | The 74HC21-Q100 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 1 | Active | The 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 1 | Active | The 74HC21-Q100 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 1 | Active | |
74HC237D-Q1003-to-8 line decoder, demultiplexer with address latches | Signal Switches, Multiplexers, Decoders | 1 | Active | The 74HC237-Q100 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237-Q100 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE= LOW), the 74HC237-Q100 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long asLEremains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unlessE1 is LOW and E2 is HIGH. The 74HC237-Q100 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. |
74HC237PW3-to-8 line decoder, demultiplexer with address latches | Logic | 1 | Active | The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE= LOW), the 74HC237 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long asLEremains HIGH. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unlessE1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobes (stored address) applications in bus-oriented systems. |
74HC2383-to-8 line decoder/demultiplexer | Integrated Circuits (ICs) | 6 | Active | The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 andE2 and E3). Every output will be LOW unlessE1 andE2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The '238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74HC238; 74HCT238 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 andE2 and E3). Every output will be LOW unlessE1 andE2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The '238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74HC238-Q100; 74HCT238-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1 andE2 and E3). Every output will be LOW unlessE1 andE2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '238 ICs and one inverter. The '238 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
