Microchip Technology

The ECC608-TFLXWPC is the [TrustFLEX](https://www.microchip.com/en-us/products/security/trust-platform/trustflex) pre-provisioned secure element part of the Microchip’s [Trust Platform](https://www.microchip.com/en-us/products/security/trust-platform) offering. The device configuration was designed to meet the secure authentication requirements mandated by the Wireless Power Consortium (WPC) Qi® 1.3 version of the standard. The ECC608-TFLXWPC configuration is defined to meet the basic authentication needs of Qi chargers that provide authentication. If so desired, dual WPC certificate slots can also be implemented. In addition, extra use cases were implemented for users who want to provide TLS authentication from the embedded system where the charger is or to provide secure boot capabilities. While some data slots are required for specific use, others provide flexibility to be used for other applications. These slot access policies will be set by the Trust Platform Design Suite tools prior to ordering the ECC608-TFLXWPC devices. This data sheet provides the slot and key configuration information that is unique to the ECC608-TFLXWPC. This information defines the access policies of each of the data zone slots. Only relevant command and I/O operating information is included. An application section discussing Microchip’s hardware and software tools that can aid in developing an application is also provided with additional links to the location of the tools. The ATECC608 offer many use cases in addition to the Qi 1.3 authentication. If Qi 1.3 is the only use case desired: * Qi 1.3 wireless charging in consumer applications, refer to the [ECC204 TrustFLEX WPC](https://ww1.microchip.com/downloads/aemDocuments/documents/SCBU/ProductDocuments/DataSheets/Trust-Platform-ECC204-TFLXWPC-Data-Sheet-DS40002471.pdf) * Qi 1.3 wireless charging in Automotive applications, refer to the [TA010](https://www.microchip.com/en-us/product/ta010). Check out our turnkey compliant [certified Qi 1.3 charger reference design](https://www.microchip.com/en-us/about/news-releases/products/new-qi_-1-3-wireless-charging-reference-design-unveiled-to-accel) to fast track your development. For automotive wireless charging applications, refer to the [TA100-VAO](https://www.microchip.com/en-us/product/TA100) Read our blogs * "[What's new in the Qi 1.3 Wireless Charging Specification and How to Ensure Secure Authentication](https://www.microchip.com/en-us/about/media-center/blog/2022/qi-wireless-charging-specification-part-1)" * "[5 Steps Process for Triggering the Key Ceremony with the Wireless Power Consortium WPC](https://www.microchip.com/en-us/about/media-center/blog/2022/5-step-process-for-triggering-the-key-ceremony)"

The ECC608 TrustMANAGER is part of the CryptoAuthenticationTM family. It's a secure authentication IC that's preconfigured and pre-provisioned with birth credentials. In others words, credentials needed to initiate the connection to the keySTREAM SaaS secured by Kudelski IoT. Once the first connection has been established with keySTREAM birth credentials, the SaaS will in-field provision the necessary custom certificates into the ECC608 TrustMANAGER. Afterwards,the keySTREAM SaaS will management the lifecycle of the certificate chain (expiry date, rotation, revocation, refurbish). Before performing the in-field provisioning, the system needs a root CA to be created. keySTREAM offers a self-service fully automated custom root CA creation, hosted and secured in Kudelski HSM. In addition to the custom root CA creation, the associated leaf certificates are also created in the keySTREAM secure HSMs before being in-field provisioned in the ECC608 TrustMANAGER.

The ECE1088 is a 28-Pin 3.3V GPIO Expansion device. The device is connected to a Master via the BC-LinkTM interface or via the SMBus.

The ECE1105 is a 48-Pin 3.3V Keyboard Scan Expansion or GPIO Expansion device. The device supports a keyboard scan matrix of 23x8 and has two PS/2 ports for touchpad and/or pointer stick support. It is connected to a Master via the SMSC BC- LinkTM interface or via the SMBus. KSI and KSO signals are multiplexed with GPIOs. **Family parts**ECE1105-HZH ECE1105I-HZH

EEC1005-UB2 is a generic, easily configurable, True Universal Backplane Management (UBM) device that can be used on hard drive backplanes to provide complete storage enclosure management and reporting to computing host systems using industry standard communication protocols. Family members are identified with a suffix of UB1 or UB2 in their ordering number, where UB1 represents the part originally ordered as simply EEC1005. UB2 devices incorporate enhancements in their functionality. EEC1005-UB2 supports a variety of host interfaces to accommodate SAS/SATS/NVMe backplane. The SFF-8654 slimline connector (Host facing Connector) can be used to route SAS signals in which case the HBA will manage SAS/SATA drives, the same connector protocol (physically a different connector) can be used to route PCIe signals in which case the HBA will manage NVME drives. In both cases UBM will be used as management protocol with support of SGPIO as well on SAS Slimline (Configuration dependent).The device supports using U.2 and U.3 Drive facing Connectors. EEC1005-UB2 also supports Multiple Backplanes on a single chassis. EEC1005-UB2 supports 2 or 3 LED IBPI blinking patterns for up to 16 drives. Customized LED blink pattern can also be programmed through the FRU. The EEC1005-UB2 has a secure boot loader that authenticates and decrypts the Flash boot image (UBM application) using the AES-256, ECDSA P-256, SHA-256 cryptographic hardware accelerators. EEC1005-UB2 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC\_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Additionally, the device offers lockable OTP storage for private keys and IDs. EEC1005-UB2 is available in 84 pin and 144 pin WFBGA packages.

The EEC1727 is a low power integrated embedded controller designed for security and storage enclosure platforms. The EEC1727 is a highly-configurable, mixed-signal, advanced I/O controller. It contains a 32-bit ARM® Cortex-M4F processor core with closely-coupled memory for optimal code execution and data access. An internal ROM, embedded in the design, is used to store the power on/boot sequence and APIs available during run time. When VTR\_CORE is applied to the device, the secure bootloader API is used to download the custom firmware image from the system’s shared SPI Flash device, thereby allowing system designers to customize the device’s behavior. The EEC1727 device is directly powered by a minimum of two separate suspend supply planes (VBAT and VTR) and senses a third runtime power plane (VCC) to provide "instant on" and system power management functions. The EEC1727 has one banks of I/O pins that are able to operate at 3.3 V (VTR1), one bank that is 1.8V (VTR3) and one bank that can operate at 3.3V/1.8V (VTR2). Operating at 1.8V allows the EEC1727 to interface with the latest platform controller hubs and will lower the overall power consumed by the device, Whereas 3.3V allows this device to be integrated into legacy platforms that require 3.3V operation. The EEC1727 secure bootloader authenticates and optionally decrypts the SPI Flash OEM boot image using the AES256, ECDSA, SHA-512 cryptographic hardware accelerators. The EEC1727 hardware accelerators support 128-bit and 256-bit AES encryption, ECDSA and EC\_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Runtime APIs are provided in the ROM for customer application code to use the cryptographic hardware. Additionally, the device offers lockable OTP storage for private keys and IDs. The EEC1727 is designed to be incorporated into low power PC architecture designs and supports ACPI sleep states (S0-S5). During normal operation, the hardware always operates in the lowest power state for a given configuration. When the chip is sleeping, it has many wake events that can be configured to return the device to normal operation. Some examples of supported wake events are PS2 wake events, RTC, Week Alarm, Hibernation Timer, or any GPIO pin. The EEC1727 offers a software development system interface that includes a Trace FIFO Debug port, a host accessible serial debug port with a 16C550A register interface, a Port 80 BIOS Debug Port, and a 2-pin Serial Wire Debug (SWD) interface. Also included is a 4-wire JTAG interface used for Boundary Scan testing.