Microchip Technology

Microsemi's WinPath3-SuperLite (WP3-SL) provides a powerful, yet lower cost WinPath3 solution for access processing in the wireline and wireless access infrastructure equipment market. This new family of devices leverages Microsemi's broad portfolio of hardened market-ready protocols and industry preferred I/O interfaces and provides this solution in devices priced less than previous WinPath devices. It has the same processing elements as the WinPath3, but a reduced number (six) running up to 400 MHz. These processing elements support the latest packet based protocols such as Ethernet, PWE3 (for Ethernet TDM, HDLC, ATM), and Packet Network Synchronization (IEEE1588v2, Synchronous Ethernet, adaptive and differential clock recovery). It also supports ML- PPP, IMA, CES, OAM (for Ethernet and ATM), QoS (policing, shaping, per-flow queuing, WRED), plus many other protocols. The WP3-SL incorporates the new WP3 hardware accelerators such as a flexible high performance classifier, a hierarchical shaper, an integrated security engine and more. The WP3-SL family broadens the Microsemi solution to include a high performance yet lower cost option providing WinPath users a program of minimum design risk and short time to market. An integrated, high performance general-purpose dual-VPE MIPS 34K processor provides on-board control path software processing. This block is a licensed core, so standard 3rd party tools such as compilers, assemblers, and EJTAG devices are fully compatible. The clock for the MIPS core is decoupled from the data path processors to better tune the system-wide control processing. A sophisticated multi-core communication engine with a large internal program RAM provides superior overall processing power plus scalability and flexibility. Being RAM based, WinComm3 can be software upgraded as protocols evolve and standards change. Original WinPath protocols are supported, plus new protocols that take advantage of the new hardware accelerators. The number of processing cores (WinGines) is limited to six. Unlike traditional network processors or other micro-coded solutions, where protocol software is located in ROM or partitioned into small, segmented micro-blocks, the WP3-SL data path software (DPS) runs from a large shared memory space, increasing flexibility and performance. This means code doesn't require prior partitioning, coherency, or order management between engines, but is handled internally through special hardware at run time. Numerous, highly flexible Ethernet options are available. Up to 24 10/100 Ethernet ports (using SMII or SS-SMII interfaces) or 6 Gigabit ports (using RGMII and SGMII interfaces) can be utilized at the same time. Additionally, 16 TDM ports support T1/ E1 or T3/E3 connectivity. Up to two UTOPIA/POS L2/ L3 ports are also available. The POS ports support 2 x SPI-3 (8-bit) as well. A single lane PCIe bus is available. Microsemi offers complete software packages enabling any-port-to-any-port routing, bridging, switching and interworking with these various interfaces. WP3-SL provides bus interfaces and memory controllers to support DDR2/DDR3 SDRAM. A large, 0.75 MBytes internal memory is used to store parameters that are frequently used. These memory controllers provide transaction optimization, auto alignment support, out of order transaction support, efficient bus utilization, and guaranteed low latency cycles which enables application level quality-of- service. On chip Error Checking and Correction (ECC) algorithms support internal as well as external memories. Several hardware accelerators supplement the WinComm3 processing resources.The Parser and Classifier Engine is able to extract fields from all the incoming packets (even in case of over- subscription), build search keys and classify the data. This not only offloads this task from WinComm3, but also allows intelligent discard decisions in case of over-subscription, bridging and routing, forwarding, ACLS, flow prioritization, and encryption flow/profile identification.The Hardware Shaper implements 3-level shaping over up to 4K queues. As an example, it is possible to classify per user, per user service, and per service level of priority. Each level can be programmed in multiple modes, including strict priority, weighted fair queuing or minimum and maximum rates for CIR and EIR shaping.A Congestion Accelerator implements WRED and tail- drop policies on up to 4K queues.The Policing Accelerator supports single and dual leaky bucket policing.The Security accelerator supports up to 1 Gbps data encryption and authentication with a variety of cryptographic engines such as AES, 3xDES, Kasumi, Snow-3G and H-MAC (SHA-1 and MD5), together with PKE. The WP3-SL Security Engine (WSE) eliminates the need for inefficient external security devices in the wireless and wireline access systems. Packet forwarding, protocol processing, and security tasks can be executed on each data quantum on the fly (even simultaneously). While a specific data unit traverses from on-chip network interfaces to external memory storage, the innovative WinPath3- SL thread processing architecture allows multiple hardware elements to process the same data unit. In this way, security tasks are performed as an integrated component of the protocol data processing and data forwarding. With this on-chip security processing, the WP3-SL can provide higher levels of overall system bandwidth while maintaining lower system cost and design complexity.The Packet Synchronization accelerator includes all hardware resources necessary to support IEEE 1588v2, Synchronous Ethernet and adaptive and differentialclock recovery for T1/E1/T3/E3. The software model consists of the Data Path Software – DPS, that runs on WinComm3, the packet processing engine and the Control Path Software – CPS that runs on the MIPS cores or and external processor connected through PCIe. Between these there is an API, the WinPath Device Driver Interface that allows control of the DPS using a simple set of high level commands. This way the application developer does not have to understand all the details of the Hardware and DPS implementation and can take advantage of the WinPath3-SL complex protocol processing resources just by enabling them through the API.Microsemi offers royalty free, production quality DPS and WDDI. New releases, typically twice per year, add new protocols that allow the software upgrade of WinPath3-SL based systems. For customers that want to include their "secret sauce" in the DPS, a source code and development tool license is available, together with qualified third parties.The current software offering includes the protocol listed in the figure below. These protocols run on WinPath-SL devices, as well as WinPath2 and WinPath3 processors, plus low-end derivatives, and use a common API. This decouples the software and hardware development, with an ever increasing selection of protocols running on different hardware platforms, providing various performance and interface options. Significant performance gains can be realized by migratng software from previous WinPath devices (WP2) to WP3-SL. These improvements require minimal changes in the API and re-compilation. However, to take advantage of WP3-SL specific hardware such as accelerators or encryption engines, new API function calls need to be activated. The WP3-SL has its own reference boards for early software development while a customer's own board is being developed. These reference boards are available in a stand-alone format as well standard AMC form factors, so they can be used with any AMC chassis. These boards are available with various I/O options to optimize these systems for a particular application. For more information, contact your respective Microsemi sales person.

The WinPath4 continues the carrier-grade Ethernet focus of its predecessors as the fourth generation of WinPath® products. Next generation protocols have been added along with a new level of performance, all the while supporting legacy applications and continuing Microchip's proven formula as a complete networking solution. The WinPath4 integrates control plane and enhanced data plane processing components. Control plane processing is based on two high-performance MIPS 34K multi-threaded processors. Data plane processing uses dedicated hardware accelerators for packet classification, hierarchical shaping, additional security standards and more to off-load common processing tasks. The accelerators are flexibly combined with a field-proven, fully-programmable, high-performance multi-threaded multi-core data path processor subsystem. 48 cores are available (up from 12 in the WinPath3) and operating speed has increased. The WinPath4 leverages a broad set of supplied protocols developed over the years and hardened in production environments all over the world. These include support for interworking (MPLS, IPv4/IPv6 Routing, VLAN-aware bridging), QoS (policing, shaping, per-flow queuing, WRED), Packet Network Synchronization (IEEE 1588v2, Synchronous Ethernet, adaptive and differential clock recovery), OAM (Ethernet, MPLS, ATM), L2 and L3 termination (Ethernet, ML-PPP, IMA, CES), PWE3 (Ethernet, TDM, HDLC, ATM) and more.

Microsemi’s MO86561 and MO86571 waveguide detectors consist of selected Schottky barrier diodes assembled in a rugged housing suitable for use in industrial applications as a RF detector. Applications- Microwave Counters Liquid Level Indicators Moisture Measurement Flow/No Flow Sensors Microwave Perimeter Protection

XIFM is an intelligent isolated Plug-and-Play mSiC™ Gate Driver designed to drive 3.3kV SiC modules in High-Voltage (HV) packages such as HV LinPak / HV100. The driver includes gate drive control, power supply, fiber optic interface and high voltage isolation (10.2 kV). **Applications** It features Augmented Switching™ to monitor the fault report and to improve control of SiC MOSFET-based power systems. * Rail Traction (Auxiliary & Propulsion systems) * Battery charging systems * Smart Grid / Grid-tied distribution generation * Uninterruptible power supply (UPS) systems * Industrial Motor drives * Heavy duty Equipment * Medium voltage chargers / Fast chargers Key driver parameters can be modified with the optional [Programming Kit and Intelligent Configuration Software](https://www.microchip.com/en-us/products/power-management/silicon-carbide-sic-devices-and-power-modules/digital-programmable-gate-drivers/intelligent-configuration-tool). We offer fast-to-market solutions to meet the demands of you and your customers, covering adaptation to full customization services. [Schedule a call with our team about gate driver customization.](https://www.microchip.com/en-us/product/microchip.my.site.com/schedulemeetingportal/s/)

The ZL30101 Stratum 3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30101 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable. The ZL30101 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

The ZL30102 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 4/4E timing specifications. The ZL30102 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining a tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter. The ZL30102 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

The ZL30105 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and timing control of redundant system clocks requiring Stratum 3 and SDH timing specifications. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between redundant primary and secondary system clocks even in the presence of high network jitter. The ZL30105 is intended to be the central timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable. The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.