Microchip Technology

The dual port VSC8582 GbE PHY with Intellisec and VeriTime is ideal for securing cloud network applications including e-commerce, databases, collaboration, smart grid, video, and enterprise or government communications. Intellisec enables a realistic and affordable Layer 2 MACsec security solution. Intellisec is a patent-pending technology enabling IEEE 802.1AE MACsec encryption end-to-end over any network, including multi-operator and cloud-based networks, independent of the network's awareness of security protocols. Intellisec is not limited to traditional MACsec link-based box-to-box applications. Likewise, Intellisec scales easily with the number of interfaces delivering significant cost savings in network deployment. VeriTime™ is Microchip's patent-pending timing technology that delivers the industry's most accurate IEEE 1588v2 timing implementation. Integration of MACsec with IEEE 1588v2 time stamping in the PHY is an efficient and low cost method to protect data passing through the network while maintaining highly accurate time of day (ToD). For these applications, the device supports daisy-chaining of SPI interfaces for IEEE 1588v2 time stamping to reduce the number of pins required on a target ASIC, SoC or FPGA. VSC8582 supports Y.1731 OAM and MPLS-TP OAM for accurate delay measurement and performance monitoring. In addition, the VSC8582 includes dual recovered clock outputs for timing references in Synchronous Ethernet solutions. Using Microchip's Ring Resiliency™ technology, the PHY switches between master and slave timing without interrupting the 1000BASE-T link. Microchip's complimentary and confidential [MicroCHECK](https://www.microchip.com/en-us/support/design-help/design-check-services) design review service, which offers insight from the initial concept to the final PCB layout, is available to customers who are using our products in their projects. You can confidently submit your design materials in a secure and private setting, and our expert engineers will provide individualized feedback to enhance your design. MicroCHECK design review service is subject to Microchip's [Program Terms and Conditions](https://www.microchip.com/en-us/support/design-help/design-check-services/design-check-services-program-terms-and-conditions) and requires a myMicrochip account.

Helping OEMs to capitalize on the cost reduction and optimization of Synchronous Ethernet (SyncE), the VSC8662 addresses the challenges in providing fully traceable timing across TDM backhaul links, cellular base stations, and other SyncE applications. With recovered clock outputs, the VSC8662 meets and goes beyond the requirements of the ITU-T recommendation G.8261/Y.1361. Supporting two copper/fiber ports and SGMII MAC interfaces, the VSC8662 includes a highly integrated feature set to ensure low-cost, rapid deployment.