Microchip Technology

The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Transceiver Logic (HSTL) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) by the CLK\_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89809AL features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). The SY89809AL is available in a single space-saving package, enabling a lower overall cost solution.

The SY89824L is a High Performance Bus Clock Driver with 22 differential HSTL (High Speed Transceiver Logic) output pairs. The part is designed for use in low voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK\_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89824L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89824L is available in a single space saving package, enabling a lower overall cost solution.

The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK\_SEL pin. The LVDS input includes a 100Ω internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The SY89825U features low pin-to-pin skew (35ps max.) --performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.

The SY89828L is a precision fanout buffer with 20 differential LVDS (Low Voltage Differential Swing) output pairs. The part is designed for use in low voltage 3.3V applications that require a large number of outputs to drive precisely aligned, ultra low-skew signals to their destination.The input is multiplexed from either LVDS or LVPECL (Low Voltage Positive Emitter Coupled Logic) by the CLK\_SEL1 and CLK\_SEL2 pins. The Output Enables (OE1 and OE2) are synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89828L features a low pin-to-pin skew of less than 50ps--performance previously unachievable in a standard product having such a high number of outputs.The SY89828L is available in a single space saving package, enabling a lower overall cost solution.

The SY89830U is a high-speed, 2.5GHz differential PECL 1:4 fanout buffer optimized for ultra-low skew applications. Within device skew is guaranteed to be less than 25ps over temperature and supply voltage. The wide supply voltage operation allows this fanout buffer to operate in 2.5V, 3.3V, and 5V systems.The SY89830U features a 2:1 input MUX, making it an ideal solution for redundant clock switchover applications. If only one input pair is used, the other pair may be left floating. In addition, this device includes a synchronous enable pin that forces the outputs into a fixed logic state. Enable or disable state is initiated only after the outputs are in a LOW state, thus eliminating the possibility of a "runt" clock pulse.The SY89830U I/O are fully differential and 100K ECL compatible. Differential 10K ECL logic can interface directly into the SY89830U inputs.The SY89830U is part of Micrel's high-speed precision edge timing and distribution family. For applications that require a different I/O combination, choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.

The SY89831U is a high-speed, 2GHz differential LVPECL 1:4 fanout buffer optimized for ultra-low skew applications. Within-device skew is guaranteed to be less than 20ps (5ps typ.) over supply voltage and temperature. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference output is included for AC-coupled applications.The SY89831U is a part of Micrel's high-speed clock synchronization family. For applications that require a different I/O combination, consult Micrel’s website and choose from a comprehensive product line of high-speed, low-skew fanout buffers, translators, and clock generators.