Diodes Inc

The 74LVC541A is an octal buffer/driver is designed for driving bus lines or buffer memory address registers. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable (OE1orOE2) input is high, all eight outputs are in the high-impedance state.

The 74LVC573A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OEdoes not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74LVC574A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74LVC86A provides four independent 2-input exclusive OR gates. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed-voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output preventing damaging current backflow when the device is powered down.

TN1.pdf

TN1.pdf

TN1.pdf

TN1.pdf

TN1.pdf