SN74LVC828A Series

10-ch, 1.65-V to 3.6-V inverters with 3-state outputs

Catalog

10-ch, 1.65-V to 3.6-V inverters with 3-state outputs

Part	Package / Case	Package / Case	Number of Bits per Element	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Output Type	Number of Elements	Current - Output High, Low	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Logic Type	Package / Case [custom]	Package / Case [custom]	Package / Case [custom]	Package / Case [custom]	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC828APW	24-TSSOP	0.173 in 4.4 mm	10	24-TSSOP	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting
Texas Instruments SN74LVC828ANSR	24-SOIC		10	24-SO	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting	5.3 mm	0.209 in
Texas Instruments SN74LVC828ADWR	24-SOIC		10	24-SOIC	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting			7.5 mm	0.295 in
Texas Instruments SN74LVC828APWR	24-TSSOP	0.173 in 4.4 mm	10	24-TSSOP	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting
Texas Instruments SN74LVC828ADGVR	24-TFSOP		10	24-TVSOP	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting					4.4 mm	0.173 in
Texas Instruments SN74LVC828ADW	24-SOIC		10	24-SOIC	85 °C	-40 °C	3-State	1	24 mA	Surface Mount	1.65 V	3.6 V	Buffer Inverting			7.5 mm	0.295 in

Catalog

10-ch, 1.65-V to 3.6-V inverters with 3-state outputs

Key Features

• Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Operates From 1.65 V to 3.6 VInputs Accept Voltages to 5.5 VMax tpdof 6.7 ns at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CSupports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2)\ input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at its outputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2)\ input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at its outputs. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.