PGA116 Series

Zero-Drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp w

Catalog

Zero-Drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp w

Part	Slew Rate	Voltage - Supply Span (Max) [Max]	Number of Circuits	Amplifier Type	Current - Output / Channel	Voltage - Input Offset	Current - Input Bias	Package / Case [y]	Package / Case	Package / Case [x]	Voltage - Supply Span (Min) [Min]	Current - Supply	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	-3db Bandwidth	Supplier Device Package	Output Type
Texas Instruments PGA116AIPW	8 V/µs	5.5 V	1	Programmable Gain	60 mA	75 µV	1.5 nA	4.4 mm	20-TSSOP	0.173 in	2.2 V	330 µA	125 °C	-40 °C	Surface Mount	10 MHz	20-TSSOP	Rail-to-Rail
Texas Instruments PGA116AIPWR	8 V/µs	5.5 V	1	Programmable Gain	60 mA	75 µV	1.5 nA	4.4 mm	20-TSSOP	0.173 in	2.2 V	330 µA	125 °C	-40 °C	Surface Mount	10 MHz	20-TSSOP	Rail-to-Rail

Catalog

Zero-Drift, 100-µV offset, 12-nV/√Hz noise, RRO (binary gain) programmable gain amp w

Key Features

• Rail-to-Rail Input and OutputOffset: 25 µV (Typical), 100 µV(Maximum)Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C(Maximum)Low Noise: 12 nV/√HzInput Offset Current: ±5 nA Maximum (25°C)Gain Error: 0.1% Maximum (G ≥ 32),0.3% Maximum (G > 32)Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,PGA116)Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200(PGA113, PGA117)Gain Switching Time: 200 ns2 Channel MUX: PGA112, PGA11310 Channel MUX: PGA116, PGA117Four Internal Calibration ChannelsAmplifier Optimized for Driving CDAC ADCsOutput Swing: 50 mV to Supply RailsAVDDand DVDDfor Mixed Voltage SystemsIQ= 1.1 mA (Typical)Software and Hardware Shutdown: IQ≤ 4 µA(Typical)Temperature Range: –40°C to 125°CSPI™ Interface (10 MHz) With Daisy-ChainCapabilityRail-to-Rail Input and OutputOffset: 25 µV (Typical), 100 µV(Maximum)Zerø Drift: 0.35 µV/°C (Typical), 1.2 µV/°C(Maximum)Low Noise: 12 nV/√HzInput Offset Current: ±5 nA Maximum (25°C)Gain Error: 0.1% Maximum (G ≥ 32),0.3% Maximum (G > 32)Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,PGA116)Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200(PGA113, PGA117)Gain Switching Time: 200 ns2 Channel MUX: PGA112, PGA11310 Channel MUX: PGA116, PGA117Four Internal Calibration ChannelsAmplifier Optimized for Driving CDAC ADCsOutput Swing: 50 mV to Supply RailsAVDDand DVDDfor Mixed Voltage SystemsIQ= 1.1 mA (Typical)Software and Hardware Shutdown: IQ≤ 4 µA(Typical)Temperature Range: –40°C to 125°CSPI™ Interface (10 MHz) With Daisy-ChainCapability

Description

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package. All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200. The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package. All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.