74HCT273BQ-Q100 Series

Octal D-type flip-flop with reset; positive-edge trigger

Manufacturer: Freescale Semiconductor - NXP

Catalog

Octal D-type flip-flop with reset; positive-edge trigger

Part	Operating Temperature [Min]	Operating Temperature [Max]	Trigger Type	Max Propagation Delay @ V, Max CL	Package / Case	Type	Input Capacitance	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Current - Quiescent (Iq)	Output Type	Number of Bits per Element	Current - Output High, Low	Number of Elements	Supplier Device Package	Clock Frequency	Qualification	Package / Case [y]	Package / Case [y]	Grade	Package / Case [x]
Freescale Semiconductor - NXP 74HCT273DB,118	-40 °C	125 °C	Positive Edge	30 ns	20-SSOP	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-SSOP	36 MHz
Freescale Semiconductor - NXP 74HCT273D-Q100J	-40 °C	125 °C	Positive Edge	30 ns	20-SOIC	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-SO	36 MHz	AEC-Q100	0.295 in	7.5 mm	Automotive
Freescale Semiconductor - NXP 74HCT273PW,112	-40 °C	125 °C	Positive Edge	30 ns	20-TSSOP	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-TSSOP	36 MHz		4.4 mm			0.173 in
Freescale Semiconductor - NXP 74HCT273DB,112	-40 °C	125 °C	Positive Edge	30 ns	20-SSOP	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-SSOP	36 MHz
Freescale Semiconductor - NXP 74HCT273BQ-Q100X	-40 °C	125 °C	Positive Edge	30 ns	20-VFQFN Exposed Pad	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-DHVQFN (4.5x2.5)	36 MHz	AEC-Q100			Automotive
Freescale Semiconductor - NXP 74HCT273BQ,115	-40 °C	125 °C	Positive Edge	30 ns	20-VFQFN Exposed Pad	D-Type	3.5 pF	4.5 V	5.5 V	Surface Mount	8 ÁA	Non-Inverted	8	4 mA 5.2 mA	1	20-DHVQFN (4.5x2.5)	36 MHz

Catalog

Octal D-type flip-flop with reset; positive-edge trigger

Key Features

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Description

The 74HC273-Q100; 74HCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.