Catalog
Quad UART with 16-Byte FIFOs
Key Features
• Integrated Asynchronous-Communications ElementConsists of Four Improved TL16C550C ACEs Plus Steering LogicIn FIFO Mode, Each ACE Transmitter and Receiver Is BufferedWith 16-Byte FIFO to Reduce the Number of Interrupts to CPUIn TL16C450 Mode, Hold and Shift Registers Eliminate Need for PreciseSynchronization Between the CPU and Serial DataUp to 16-MHz Clock Rate for up to 1-Mbaud Operation with VCC= 3.3 V and 5 VProgrammable Baud-Rate Generators Which Allow Division of Any Input Reference Clockby 1 to (216– 1) and Generate an Internal 16 × ClockAdds or Deletes Standard Asynchronous Communication Bits (Start, Stop, andParity) to or From the Serial-Data StreamIndependently Controlled Transmit, Receive, Line Status, and Data Set Interrupts5-V and 3.3-V OperationFully Programmable Serial Interface Characteristics:5-, 6-, 7-, or 8-Bit CharactersEven-, Odd-, or No-Parity Bit1-, 1 1/2-, or 2-Stop Bit GenerationBaud Generation (DC to 1-Mbit Per Second)False Start Bit DetectionComplete Status Reporting CapabilitiesLine Break Generation and DetectionInternal Diagnostic Capabilities:Loopback Controls for Communications Link Fault IsolationBreak, Parity, Overrun, Framing Error SimulationFully Prioritized Interrupt System ControlsModem Control Functions (CTS,RTS,DSR,DTR,RI, andDCD)3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Busand Control BusProgrammable Auto-RTSand Auto-CTSCTSControls Transmitter in Auto-CTSMode,RCV FIFO Contents and Threshold ControlRTSin Auto-RTSMode,Integrated Asynchronous-Communications ElementConsists of Four Improved TL16C550C ACEs Plus Steering LogicIn FIFO Mode, Each ACE Transmitter and Receiver Is BufferedWith 16-Byte FIFO to Reduce the Number of Interrupts to CPUIn TL16C450 Mode, Hold and Shift Registers Eliminate Need for PreciseSynchronization Between the CPU and Serial DataUp to 16-MHz Clock Rate for up to 1-Mbaud Operation with VCC= 3.3 V and 5 VProgrammable Baud-Rate Generators Which Allow Division of Any Input Reference Clockby 1 to (216– 1) and Generate an Internal 16 × ClockAdds or Deletes Standard Asynchronous Communication Bits (Start, Stop, andParity) to or From the Serial-Data StreamIndependently Controlled Transmit, Receive, Line Status, and Data Set Interrupts5-V and 3.3-V OperationFully Programmable Serial Interface Characteristics:5-, 6-, 7-, or 8-Bit CharactersEven-, Odd-, or No-Parity Bit1-, 1 1/2-, or 2-Stop Bit GenerationBaud Generation (DC to 1-Mbit Per Second)False Start Bit DetectionComplete Status Reporting CapabilitiesLine Break Generation and DetectionInternal Diagnostic Capabilities:Loopback Controls for Communications Link Fault IsolationBreak, Parity, Overrun, Framing Error SimulationFully Prioritized Interrupt System ControlsModem Control Functions (CTS,RTS,DSR,DTR,RI, andDCD)3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Busand Control BusProgrammable Auto-RTSand Auto-CTSCTSControls Transmitter in Auto-CTSMode,RCV FIFO Contents and Threshold ControlRTSin Auto-RTSMode,
Description
AI
The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow usingRTSoutput andCTSinput signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 216– 1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.
The TL16C554A is an enhanced quadruple version of the TL16C550C asynchronous-communications element (ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the quadruple ACE can be read by the CPU at any time during operation. The information obtained includes the type and condition of the operation performed and any error conditions encountered.
The TL16C554A quadruple ACE can be placed in an alternate FIFO mode, which activates the internal FIFOs to allow 16 bytes (plus three bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. In the FIFO mode of operation, there is a selectable autoflow control feature that can significantly reduce software overhead and increase system efficiency by automatically controlling serial-data flow usingRTSoutput andCTSinput signals. All logic is on the chip to minimize system overhead and maximize system efficiency. Two terminal functions allow signaling of direct-memory access (DMA) transfers. Each ACE includes a programmable baud-rate generator that can divide the timing reference clock input by a divisor between 1 and 216– 1.
The TL16C554A is available in a 68-pin plastic-leaded chip-carrier (PLCC) FN package, 64-pin plastic quad flatpack (PQFP) PM package and in an 80-pin (TQFP) PN package.
