DRA76P Series

High performance multi-core SoC processors with ISP for digital cockpit applications

Catalog

High performance multi-core SoC processors with ISP for digital cockpit applications

Part	Voltage - I/O	SATA	RAM Controllers	Core Processor	Graphics Acceleration	Ethernet	Speed	Operating Temperature [Min]	Operating Temperature [Max]	Additional Interfaces	Package / Case	USB	Qualification	Number of Cores/Bus Width [custom]	Number of Cores/Bus Width [custom]	Grade	Mounting Type	Security Features	Display & Interface Controllers	Co-Processors/DSP
Texas Instruments DRA767PSGACDRQ1	1.35 V 1.5 V 1.8 V 3.3 V	3 Gbps	DDR2 DDR3 DDR3L	ARM® Cortex®-A15		1 Gbps	1.8 GHz	-40 °C	125 ¯C	CANbus DMA I2C I2S IrDA McASP McSPI MMC/SD/SDIO PCIe QSPI TDM UART	784-LFBGA FCBGA	USB 2.0 (3) USB 3.0 (1)	AEC-Q100	32 Bit	2	Automotive	Surface Mount	Boot Security Cryptography Device Identity Isolation Firewalls Secure Debug Secure Storage Software IP Protection	DVI HDMI LCD	ARM® Cortex®-M4 C66x IVA

Catalog

High performance multi-core SoC processors with ISP for digital cockpit applications

Key Features

• Architecture Designed for Infotainment ApplicationsVideo, Image, and Graphics Processing SupportFull-HD Video (1920 × 1080p, 60 fps)Multiple Video Input and Video Output2D and 3D GraphicsDual Arm®Cortex®-A15 Microprocessor SubsystemUp to Two C66x Floating-Point VLIW DSPFully Object-Code Compatible with C67x and C64x+Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per CycleUp to 2.5MB of On-Chip L3 RAMLevel 3 (L3) and Level 4 (L4) InterconnectsTwo DDR2/DDR3/DDR3L Memory Interface (EMIF) ModulesSupports up to DDR2-800 and DDR3-1333Up to 2GB Supported per EMIFDual ARM® Cortex®-M4 Image Processing Units (IPU)Up to Two Embedded Vision Engines (EVEs)Imaging Subsystem (ISS)Image Signal Processor (ISP)Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)One Camera Adaptation Layer (CAL_B)IVA SubsystemDisplay SubsystemDisplay Controller with DMA Engine and up to Three PipelinesHDMI™ Encoder: HDMI 1.4a and DVI 1.0 CompliantVideo Processing Engine (VPE)2D-Graphics Accelerator (BB2D) SubsystemVivante®GC320 CoreDual-Core PowerVR®SGX544 3D GPUTwo Video Input Port (VIP) ModulesSupport for up to Eight Multiplexed Input PortsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) Controller2-Port Gigabit Ethernet (GMAC)Sixteen 32-Bit General-Purpose Timers32-Bit MPU Watchdog TimerFive Inter-Integrated Circuit (I2C) PortsHDQ™/1-Wire®InterfaceSATA InterfaceMedia Local Bus (MLB) SubsystemTen Configurable UART/IrDA/CIR ModulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad SPI (QSPI)Eight Multichannel Audio Serial Port (McASP) ModulesSuperSpeed USB 3.0 Dual-Role DeviceThree High-Speed USB 2.0 Dual-Role DevicesFour MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)PCI Express®3.0 Subsystems with Two 5-Gbps LanesOne 2-Lane Gen2-Compliant Portor Two 1-Lane Gen2-Compliant PortsUp to Two Controller Area Network (DCAN) ModulesCAN 2.0B ProtocolModular Controller Area Network (MCAN) ModuleCAN 2.0B Protocol with Available FD (Flexible Data Rate) FunctionalityMIPI CSI-2 Camera Serial InterfaceUp to 247 General-Purpose I/O (GPIO) PinsDevice Security FeaturesHardware Crypto Accelerators and DMAFirewallsJTAG®LockSecure KeysSecure ROM and BootCustomer Programmable Keys and OTP DataPower, Reset, and Clock ManagementOn-Chip Debug with CTools Technology28-nm CMOS Technology23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)Architecture Designed for Infotainment ApplicationsVideo, Image, and Graphics Processing SupportFull-HD Video (1920 × 1080p, 60 fps)Multiple Video Input and Video Output2D and 3D GraphicsDual Arm®Cortex®-A15 Microprocessor SubsystemUp to Two C66x Floating-Point VLIW DSPFully Object-Code Compatible with C67x and C64x+Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per CycleUp to 2.5MB of On-Chip L3 RAMLevel 3 (L3) and Level 4 (L4) InterconnectsTwo DDR2/DDR3/DDR3L Memory Interface (EMIF) ModulesSupports up to DDR2-800 and DDR3-1333Up to 2GB Supported per EMIFDual ARM® Cortex®-M4 Image Processing Units (IPU)Up to Two Embedded Vision Engines (EVEs)Imaging Subsystem (ISS)Image Signal Processor (ISP)Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)One Camera Adaptation Layer (CAL_B)IVA SubsystemDisplay SubsystemDisplay Controller with DMA Engine and up to Three PipelinesHDMI™ Encoder: HDMI 1.4a and DVI 1.0 CompliantVideo Processing Engine (VPE)2D-Graphics Accelerator (BB2D) SubsystemVivante®GC320 CoreDual-Core PowerVR®SGX544 3D GPUTwo Video Input Port (VIP) ModulesSupport for up to Eight Multiplexed Input PortsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) Controller2-Port Gigabit Ethernet (GMAC)Sixteen 32-Bit General-Purpose Timers32-Bit MPU Watchdog TimerFive Inter-Integrated Circuit (I2C) PortsHDQ™/1-Wire®InterfaceSATA InterfaceMedia Local Bus (MLB) SubsystemTen Configurable UART/IrDA/CIR ModulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad SPI (QSPI)Eight Multichannel Audio Serial Port (McASP) ModulesSuperSpeed USB 3.0 Dual-Role DeviceThree High-Speed USB 2.0 Dual-Role DevicesFour MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)PCI Express®3.0 Subsystems with Two 5-Gbps LanesOne 2-Lane Gen2-Compliant Portor Two 1-Lane Gen2-Compliant PortsUp to Two Controller Area Network (DCAN) ModulesCAN 2.0B ProtocolModular Controller Area Network (MCAN) ModuleCAN 2.0B Protocol with Available FD (Flexible Data Rate) FunctionalityMIPI CSI-2 Camera Serial InterfaceUp to 247 General-Purpose I/O (GPIO) PinsDevice Security FeaturesHardware Crypto Accelerators and DMAFirewallsJTAG®LockSecure KeysSecure ROM and BootCustomer Programmable Keys and OTP DataPower, Reset, and Clock ManagementOn-Chip Debug with CTools Technology28-nm CMOS Technology23 mm × 23 mm, 0.8-mm Pitch, 784-Pin BGA (ACD)

Description

DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences. The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set. Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA77xP and DRA76xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard. DRA77x and DRA76x (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences. The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set. Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA77x and DRA76x Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard. DRA77xP and DRA76xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences. The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set. Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA77xP and DRA76xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard. DRA77x and DRA76x (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences. The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set. Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA77x and DRA76x Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.