SN74AUP2G08 Series

2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

Catalog

2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

Part	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Current - Quiescent (Max) [Max]	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Mounting Type	Number of Inputs	Supplier Device Package	Number of Circuits	Logic Type	Max Propagation Delay @ V, Max CL	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments SN74AUP2G08RSER	85 °C	-40 °C	8-UFQFN	500 nA	2 V	1.6 V	Surface Mount	2	8-UQFN (1.5x1.5)	2	AND Gate	6.7 ns	4 mA	4 mA	0.8 V	3.6 V
Texas Instruments SN74AUP2G08YFPR	85 °C	-40 °C	8-XFBGA DSBGA	500 nA	2 V	1.6 V	Surface Mount	2	8-DSBGA	2	AND Gate	6.7 ns	4 mA	4 mA	0.8 V	3.6 V

Catalog

2-ch, 2-input 0.8-V to 3.6-V low power (< 1uA) AND gate

Key Features

• Wide operating VCC range of 0.8V to 3.6VLow static-power consumption (ICC = 0.9µA max)Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)Low noise – overshoot and undershoot <10% of VCCIoff supports partial-power-down mode operationSchmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)3.6V I/O tolerant to support mixed-mode signal operationtpd = 5.9ns max at 3.3VLatch-up performance exceeds 100mA per JESD 78, Class IIWide operating VCC range of 0.8V to 3.6VLow static-power consumption (ICC = 0.9µA max)Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)Low noise – overshoot and undershoot <10% of VCCIoff supports partial-power-down mode operationSchmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)3.6V I/O tolerant to support mixed-mode signal operationtpd = 5.9ns max at 3.3VLatch-up performance exceeds 100mA per JESD 78, Class II

Description

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down. This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.