Catalog
Octal 25-Ohm Bus Transceivers
Key Features
• State-of-the-Art BiCMOS Design Significantly Reduces ICCZDesigned to Facilitate Incident-Wave Switching for Line Impedances of 25or GreaterDistributed VCCand GND Pins Minimize Noise Generated by the Simultaneous Switching of OutputsData Flow-Through Pinout (All Inputs on Opposite Side From Outputs)High-Impedance State During Power Up and Power DownESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)State-of-the-Art BiCMOS Design Significantly Reduces ICCZDesigned to Facilitate Incident-Wave Switching for Line Impedances of 25or GreaterDistributed VCCand GND Pins Minimize Noise Generated by the Simultaneous Switching of OutputsData Flow-Through Pinout (All Inputs on Opposite Side From Outputs)High-Impedance State During Power Up and Power DownESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
Description
AI
The SN64BCT25245 is a 25-octal bus transceiver designed for asynchronous communication between data buses. It improves both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable () input can disable the device so that both buses are effectively isolated.
This transceiver is capable of sinking 188-mA IOL, which facilitates switching 25-transmission lines on the incident wave. The distributed VCCand GND pins minimize switching noise for more reliable system operation.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.
The SN64BCT25245 is characterized for operation from -40°C to 85°C and 0°C to 70°C.
The SN64BCT25245 is a 25-octal bus transceiver designed for asynchronous communication between data buses. It improves both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable () input can disable the device so that both buses are effectively isolated.
This transceiver is capable of sinking 188-mA IOL, which facilitates switching 25-transmission lines on the incident wave. The distributed VCCand GND pins minimize switching noise for more reliable system operation.
The outputs are in a high-impedance state during power up and power down while the supply voltage is less than approximately 3 V.
The SN64BCT25245 is characterized for operation from -40°C to 85°C and 0°C to 70°C.
