CD40161B Series

CMOS Synchronous Programmable 4-Bit Binary Counter with Asynchronous Clear

Catalog

CMOS Synchronous Programmable 4-Bit Binary Counter with Asynchronous Clear

Part	Timing	Supplier Device Package	Mounting Type	Number of Elements	Count Rate	Operating Temperature [Min]	Operating Temperature [Max]	Direction	Reset	Number of Bits per Element	Logic Type	Trigger Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Package / Case	Package / Case	Package / Case [x]	Package / Case [y]
Texas Instruments CD40161BNSR	Synchronous	16-SO	Surface Mount	1	8 MHz	-55 °C	125 °C	Up	Asynchronous	4	Binary Counter	Positive Edge	18 V	3 V	0.209 "	16-SOIC	5.3 mm
Texas Instruments CD40161BNS
Texas Instruments CD40161BPWR	Synchronous	16-TSSOP	Surface Mount	1	8 MHz	-55 °C	125 °C	Up	Asynchronous	4	Binary Counter	Positive Edge	18 V	3 V		16-TSSOP		0.173 in	4.4 mm
Texas Instruments CD40161BPWG4	Synchronous	16-TSSOP	Surface Mount	1	8 MHz	-55 °C	125 °C	Up	Asynchronous	4	Binary Counter	Positive Edge	18 V	3 V		16-TSSOP		0.173 in	4.4 mm
Texas Instruments CD40161BE	Synchronous	16-PDIP	Through Hole	1	8 MHz	-55 °C	125 °C	Up	Asynchronous	4	Binary Counter	Positive Edge	18 V	3 V	0.3 in	16-DIP	7.62 mm
Texas Instruments CD40161BPW	Synchronous	16-TSSOP	Surface Mount	1	8 MHz	-55 °C	125 °C	Up	Asynchronous	4	Binary Counter	Positive Edge	18 V	3 V		16-TSSOP		0.173 in	4.4 mm

Catalog

CMOS Synchronous Programmable 4-Bit Binary Counter with Asynchronous Clear

Key Features

• Internal look-ahead for fast countingCarry output for cascadingSynchronously programmableClear asynchronous input (CD40160B, CD40161B)Clear synchronous input (CD40162B, CD40163B)Synchronous load control inputLow-power TTL compatibilityStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"ApplicationsProgrammable binary and decade countingCounter control/timersFrequency dividingData sheet acquired from Harris SemiconductorCD40160B - Decade with Asynchronous ClearCD40161B - Binary with Asynchronous ClearCD40162B - Decade with Synchronous ClearCD40163B - Binary with Synchronous ClearCD40160B, CD40162B, and CD40163B were not acquired from Harris Semiconductor.Internal look-ahead for fast countingCarry output for cascadingSynchronously programmableClear asynchronous input (CD40160B, CD40161B)Clear synchronous input (CD40162B, CD40163B)Synchronous load control inputLow-power TTL compatibilityStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (full package temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"ApplicationsProgrammable binary and decade countingCounter control/timersFrequency dividingData sheet acquired from Harris SemiconductorCD40160B - Decade with Asynchronous ClearCD40161B - Binary with Asynchronous ClearCD40162B - Decade with Synchronous ClearCD40163B - Binary with Synchronous ClearCD40160B, CD40162B, and CD40163B were not acquired from Harris Semiconductor.

Description

CD40160B, CD40161B, CD40162B, and CD40163B are 4-bit synchronous programmable counters. The CLEAR function of the CD40162B and CD40163B is synchronous and a low level at the CLEAR\ input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160B and CD40161B is asynchronous and a low level at the CLEAR\ input sets all four outputs low regardless of the state of the CLOCK, LOAD\, or ENABLE inputs. A low level at the LOAD\ input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low. The CD40160B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). The CD40161B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40160B through CD40163B types are functionally equivalent to and pin-compatible with the TTL counter series 74LS160 through 74LS163 respectively. CD40160B, CD40161B, CD40162B, and CD40163B are 4-bit synchronous programmable counters. The CLEAR function of the CD40162B and CD40163B is synchronous and a low level at the CLEAR\ input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160B and CD40161B is asynchronous and a low level at the CLEAR\ input sets all four outputs low regardless of the state of the CLOCK, LOAD\, or ENABLE inputs. A low level at the LOAD\ input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low. The CD40160B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). The CD40161B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). The CD40160B through CD40163B types are functionally equivalent to and pin-compatible with the TTL counter series 74LS160 through 74LS163 respectively.