DAC5687-EP Series

Enhanced Product, Dual-Channel, 16-Bit, 500-MSPS, 1x-8x Interpolating Digital-to-Analog Converter

Catalog

Enhanced Product, Dual-Channel, 16-Bit, 500-MSPS, 1x-8x Interpolating Digital-to-Analog Converter

Part	Output Type	Architecture	Package / Case	Reference Type	Number of Bits	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	INL/DNL (LSB)	Supplier Device Package	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Settling Time	Data Interface	DAC Type	Sampling Rate (Per Second)	Number of DAC's	Utilized IC / Part	Supplied Contents	INL/DNL (LSB)
Texas Instruments DAC5687IPZPG4	Current - Unbuffered	Current Sink	100-TQFP Exposed Pad	External Internal	16	3.6 V	3 V	4 LSB	100-HTQFP (14x14)	1.71 V	2.15 V	Surface Mount	85 °C	-40 °C	10.4 ns	Parallel
Texas Instruments DAC5687EVM					16										10.4 ns	Parallel	Current	500 M	2	DAC5687	Board(s)
Texas Instruments DAC5687MPZPEP	Current - Unbuffered	Current Sink	100-TQFP Exposed Pad	External Internal	16	3.6 V	3 V		100-HTQFP (14x14)	1.71 V	2.15 V	Surface Mount	125 °C	-55 °C	10.4 ns	Serial						±4 ±5

Catalog

Enhanced Product, Dual-Channel, 16-Bit, 500-MSPS, 1x-8x Interpolating Digital-to-Analog Converter

Key Features

• Controlled BaselineOne AssemblyOne Test SiteOne Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product–Change NotificationQualification Pedigree(1)500 MSPSSelectable 2×–8× InterpolationOn–Chip PLL/VCO Clock MultiplierFull IQ Compensation Including Offset, Gain, and PhaseFlexible Input OptionsFIFO With Latch on External or Internal ClockEven/Odd Multiplexed InputSingle–Port Demultiplexed InputComplex Mixer With 32–Bit Numerically Controlled Oscillator (NCO)Fixed–Frequency Mixer With Fs/4 and Fs/21.8–V or 3.3–V I/O VoltageOn–Chip 1.2–V ReferenceDifferential Scalable Output: 2 mA to 20 mAPin Compatible to DAC5686High Performance81–dBc Adjacent Channel Leakage Ratio (ACLR) WCDMA TM1 at 30.72 MHz72–dBc ACLR WCDMA TM1 at 153.6 MHzPackage: 100–Pin HTQFPAPPLICATIONSCellular Base Transceiver Station Transmit ChannelCDMA: W–CDMA, CDMA2000, TD–SCDMATDMA: GSM, IS–136, EDGE/UWC–136OFDM: 802.16Cable Modem Termination System(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne AssemblyOne Test SiteOne Fabrication SiteExtended Temperature Performance of –55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product–Change NotificationQualification Pedigree(1)500 MSPSSelectable 2×–8× InterpolationOn–Chip PLL/VCO Clock MultiplierFull IQ Compensation Including Offset, Gain, and PhaseFlexible Input OptionsFIFO With Latch on External or Internal ClockEven/Odd Multiplexed InputSingle–Port Demultiplexed InputComplex Mixer With 32–Bit Numerically Controlled Oscillator (NCO)Fixed–Frequency Mixer With Fs/4 and Fs/21.8–V or 3.3–V I/O VoltageOn–Chip 1.2–V ReferenceDifferential Scalable Output: 2 mA to 20 mAPin Compatible to DAC5686High Performance81–dBc Adjacent Channel Leakage Ratio (ACLR) WCDMA TM1 at 30.72 MHz72–dBc ACLR WCDMA TM1 at 153.6 MHzPackage: 100–Pin HTQFPAPPLICATIONSCellular Base Transceiver Station Transmit ChannelCDMA: W–CDMA, CDMA2000, TD–SCDMATDMA: GSM, IS–136, EDGE/UWC–136OFDM: 802.16Cable Modem Termination System(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

The DAC5687 is a dual–channel 16–bit high–speed digital–to–analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), on–board clock multiplier, IQ compensation, and on–chip voltage reference. The DAC5687 is pin compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and phase-locked loop (PLL) noise performance. The DAC5687 has six signal processing blocks: two interpolate by two digital filters, a fine–frequency mixer with 32–bit NCO, a quadrature modulation compensation block, another interpolate by two digital filter, and a coarse–frequency mixer with Fs/2 or Fs/4. The different modes of operation enable or bypass the signal processing blocks. The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert Transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single sideband upconversion. The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator. The DAC5687 includes several input options: single–port interleaved data, even and odd multiplexing at half rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate. The DAC5687 is a dual–channel 16–bit high–speed digital–to–analog converter (DAC) with integrated 2×, 4×, and 8× interpolation filters, a complex numerically controlled oscillator (NCO), on–board clock multiplier, IQ compensation, and on–chip voltage reference. The DAC5687 is pin compatible to the DAC5686, requiring only changes in register settings for most applications, and offers additional features and superior linearity, noise, crosstalk, and phase-locked loop (PLL) noise performance. The DAC5687 has six signal processing blocks: two interpolate by two digital filters, a fine–frequency mixer with 32–bit NCO, a quadrature modulation compensation block, another interpolate by two digital filter, and a coarse–frequency mixer with Fs/2 or Fs/4. The different modes of operation enable or bypass the signal processing blocks. The coarse and fine mixers can be combined to span a wider range of frequencies with fine resolution. The DAC5687 allows both complex or real output. Combining the frequency upconversion and complex output produces a Hilbert Transform pair that is output from the two DACs. An external RF quadrature modulator then performs the final single sideband upconversion. The IQ compensation feature allows optimization of phase, gain, and offset to maximize sideband rejection and minimize LO feedthrough for an analog quadrature modulator. The DAC5687 includes several input options: single–port interleaved data, even and odd multiplexing at half rate, and an input FIFO with either external or internal clock to ease the input timing ambiguity when the DAC5687 is clocked at the DAC output sample rate.