AM3517 Series

Sitara processor: Arm Cortex-A8, 3D graphics, video front end

Catalog

Sitara processor: Arm Cortex-A8, 3D graphics, video front end

Part	Ethernet	Ethernet [Max]	Ethernet [Min]	Number of Cores/Bus Width	Operating Temperature [Min]	Operating Temperature [Max]	Core Processor	Speed	Display & Interface Controllers	Package / Case	Security Features	Supplier Device Package	Co-Processors/DSP	Additional Interfaces	RAM Controllers	Mounting Type	Voltage - I/O	USB	Operating Temperature [custom]
Texas Instruments AM3517AZERC	1	100 Mbps	10 Mbps	1 Core 32 Bit	0 °C	90 °C	ARM® Cortex®-A8	600 MHz	LCD	484-BBGA Exposed Pad	Cryptography	484-BGA (23x23)	Multimedia NEON™ SIMD	CAN HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	DDR2 LPDDR	Surface Mount	1.8 V 3.3 V	USB 2.0 (3) USB 2.0 + PHY (1)
Texas Instruments AM3517AZERA	1	100 Mbps	10 Mbps	1 Core 32 Bit			ARM® Cortex®-A8	600 MHz	LCD	484-BBGA Exposed Pad		484-BGA (23x23)	Multimedia NEON™ SIMD	CAN HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	DDR2 LPDDR	Surface Mount	1.8 V 3.3 V	USB 2.0 (3) USB 2.0 + PHY (1)	-40 °C 105 °C
Texas Instruments AM3517AZCN	1	100 Mbps	10 Mbps	1 Core 32 Bit	0 °C	90 °C	ARM® Cortex®-A8	600 MHz	LCD	491-LFBGA		491-NFBGA (17x17)	Multimedia NEON™ SIMD	CAN HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	DDR2 LPDDR	Surface Mount	1.8 V 3.3 V	USB 2.0 (3) USB 2.0 + PHY (1)
Texas Instruments AM3517AZCNAC	1	100 Mbps	10 Mbps	1 Core 32 Bit			ARM® Cortex®-A8	600 MHz	LCD	491-LFBGA	Cryptography	491-NFBGA (17x17)	Multimedia NEON™ SIMD	CAN HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	DDR2 LPDDR	Surface Mount	1.8 V 3.3 V	USB 2.0 (3) USB 2.0 + PHY (1)	-40 °C 105 °C
Texas Instruments AM3517AZCNA	1	100 Mbps	10 Mbps	1 Core 32 Bit			ARM® Cortex®-A8	600 MHz	LCD	491-LFBGA		491-NFBGA (17x17)	Multimedia NEON™ SIMD	CAN HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	DDR2 LPDDR	Surface Mount	1.8 V 3.3 V	USB 2.0 (3) USB 2.0 + PHY (1)	-40 °C 105 °C

Catalog

Sitara processor: Arm Cortex-A8, 3D graphics, video front end

Key Features

• AM3517/05 Sitara Processor:MPU Subsystem600-MHz Sitara ARM Cortex-A8 CoreNEON SIMD Coprocessor and VectorFloating-Point (FP) CoprocessorMemory Interfaces:166-MHz 16- and 32-Bit mDDR/DDR2Interface with 1GB of Total AddressableSpaceUp to 83 MHz General-Purpose MemoryInterface Supporting 16-Bit-WideMultiplexed Address/DataBus64KB of SRAM3 Removable Media Interfaces[MMC/SD/SDIO]IO Voltage:mDDR/DDR2 IOs: 1.8VOther IOs: 1.8V and 3.3VCore Voltage: 1.2VCommercial and Extended Temperature Grade(operating restrictions apply)16-Bit Video Input Port Capable ofCapturing HD VideoHD Resolution Display SubsystemSerial CommunicationHigh-End CAN Controller10/100 Mbit Ethernet MACUSB OTG Subsystem with StandardDP/DM Interface [HS/FS/LS]Multiport USB Host Subsystem [HS/FS/LS]12-Pin ULPI or 6-, 4-, or 3-Pin SerialInterfaceFour Master and Slave Multichannel SerialPort Interface(McSPI) PortsFive Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer(McBSP1/3/4/5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 andMcBSP3 Only)For Filter, Gain, and MixOperations128-Channel Transmit and Receive ModeDirect Interface to I2S and PCM Device andTDM BusesHDQ/1-Wire Interface4 UARTs (One with Infrared Data Association[IrDA] and Consumer Infrared [CIR] Modes)3 Master and Slave High-Speed Inter-IntegratedCircuit (I2C) ControllersTwelve 32-bit General-Purpose TimersOne 32-bit Watchdog TimerOne 32-bit 32-kHz Sync TimerUp to 186 General-Purpose I/O (GPIO) PinsDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI)LCD PanelsTwo 10-Bit Digital-to-Analog Converters (DACs)SupportingComposite NTSC/PAL VideoLuma/Chroma Separate Video (S-Video)Rotation of 90, 180, and 270 DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingVideo Processing Front End (VPFE) 16-Bit Video Input PortRAW Data Interface75-MHz Maximum Pixel ClockSupports REC656/CCIR656 StandardSupports YCbCr422 Format (8-Bit or 16-Bit with DiscreteHorizontal and Vertical Sync Signals)Generates Optical Black Clamping SignalsBuilt-in Digital Clamping and Black Level Compensation10-Bit to 8-Bit A-law Compression HardwareSupports up to 16K Pixels (Image Size) in Horizontaland Vertical DirectionsSystem Direct Memory Access (sDMA) Controller (32 LogicalChannels with Configurable Priority)Comprehensive Power, Reset, and Clock ManagementARM Cortex-A8 Memory ArchitectureARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Microprocessor CoreARM NEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target AddressCache, Global History Buffer and 8-Entry Return StackEmbedded Trace Macrocell [ETM] Support forNoninvasive Debug16KB of Instruction Cache (4-Way Set-Associative)16KB of Data Cache (4-Way Set-Associative)256KB of L2 CachePowerVR SGX Graphics Accelerator (AM3517 Only)Tile-Based Architecture Delivering up to 10 MPoly/secUniversal Scalable Shader Engine: Multi-threaded EngineIncorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, andPower ManagementProgrammable, High-Quality Image Anti-AliasingEndianessARM Instructions – Little EndianARM Data – ConfigurableSDRC Memory Controller16- and 32-Bit Memory Controller with 1GB ofTotal Address SpaceDouble Data Rate (DDR2) SDRAM, Mobile Double Data Rate(mDDR)SDRAMSDRAM Memory Scheduler (SMS) and Rotation EngineGeneral Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address/Data BusUp to 8 Chip-Select Pins with 128MB of AddressSpace per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECCHamming Code Calculation), SRAM and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interfaceto Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address/Data Mode (Limited 2-KBAddress Space)Test InterfacesIEEE-1149.1 (JTAG) Boundary-Scan CompatibleEmbedded Trace Macro Interface (ETM)65-nm CMOS TechnologyPackages:491-Pin BGA (17 x 17, 0.65-mm Pitch)[ZCN Suffix]with Via Channel ArrayTechnology484-Pin PBGA (23 x 23, 1-mm Pitch)[ZER Suffix]AM3517/05 Sitara Processor:MPU Subsystem600-MHz Sitara ARM Cortex-A8 CoreNEON SIMD Coprocessor and VectorFloating-Point (FP) CoprocessorMemory Interfaces:166-MHz 16- and 32-Bit mDDR/DDR2Interface with 1GB of Total AddressableSpaceUp to 83 MHz General-Purpose MemoryInterface Supporting 16-Bit-WideMultiplexed Address/DataBus64KB of SRAM3 Removable Media Interfaces[MMC/SD/SDIO]IO Voltage:mDDR/DDR2 IOs: 1.8VOther IOs: 1.8V and 3.3VCore Voltage: 1.2VCommercial and Extended Temperature Grade(operating restrictions apply)16-Bit Video Input Port Capable ofCapturing HD VideoHD Resolution Display SubsystemSerial CommunicationHigh-End CAN Controller10/100 Mbit Ethernet MACUSB OTG Subsystem with StandardDP/DM Interface [HS/FS/LS]Multiport USB Host Subsystem [HS/FS/LS]12-Pin ULPI or 6-, 4-, or 3-Pin SerialInterfaceFour Master and Slave Multichannel SerialPort Interface(McSPI) PortsFive Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer(McBSP1/3/4/5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 andMcBSP3 Only)For Filter, Gain, and MixOperations128-Channel Transmit and Receive ModeDirect Interface to I2S and PCM Device andTDM BusesHDQ/1-Wire Interface4 UARTs (One with Infrared Data Association[IrDA] and Consumer Infrared [CIR] Modes)3 Master and Slave High-Speed Inter-IntegratedCircuit (I2C) ControllersTwelve 32-bit General-Purpose TimersOne 32-bit Watchdog TimerOne 32-bit 32-kHz Sync TimerUp to 186 General-Purpose I/O (GPIO) PinsDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI)LCD PanelsTwo 10-Bit Digital-to-Analog Converters (DACs)SupportingComposite NTSC/PAL VideoLuma/Chroma Separate Video (S-Video)Rotation of 90, 180, and 270 DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingVideo Processing Front End (VPFE) 16-Bit Video Input PortRAW Data Interface75-MHz Maximum Pixel ClockSupports REC656/CCIR656 StandardSupports YCbCr422 Format (8-Bit or 16-Bit with DiscreteHorizontal and Vertical Sync Signals)Generates Optical Black Clamping SignalsBuilt-in Digital Clamping and Black Level Compensation10-Bit to 8-Bit A-law Compression HardwareSupports up to 16K Pixels (Image Size) in Horizontaland Vertical DirectionsSystem Direct Memory Access (sDMA) Controller (32 LogicalChannels with Configurable Priority)Comprehensive Power, Reset, and Clock ManagementARM Cortex-A8 Memory ArchitectureARMv7 ArchitectureIn-Order, Dual-Issue, Superscalar Microprocessor CoreARM NEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target AddressCache, Global History Buffer and 8-Entry Return StackEmbedded Trace Macrocell [ETM] Support forNoninvasive Debug16KB of Instruction Cache (4-Way Set-Associative)16KB of Data Cache (4-Way Set-Associative)256KB of L2 CachePowerVR SGX Graphics Accelerator (AM3517 Only)Tile-Based Architecture Delivering up to 10 MPoly/secUniversal Scalable Shader Engine: Multi-threaded EngineIncorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, andPower ManagementProgrammable, High-Quality Image Anti-AliasingEndianessARM Instructions – Little EndianARM Data – ConfigurableSDRC Memory Controller16- and 32-Bit Memory Controller with 1GB ofTotal Address SpaceDouble Data Rate (DDR2) SDRAM, Mobile Double Data Rate(mDDR)SDRAMSDRAM Memory Scheduler (SMS) and Rotation EngineGeneral Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address/Data BusUp to 8 Chip-Select Pins with 128MB of AddressSpace per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECCHamming Code Calculation), SRAM and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interfaceto Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address/Data Mode (Limited 2-KBAddress Space)Test InterfacesIEEE-1149.1 (JTAG) Boundary-Scan CompatibleEmbedded Trace Macro Interface (ETM)65-nm CMOS TechnologyPackages:491-Pin BGA (17 x 17, 0.65-mm Pitch)[ZCN Suffix]with Via Channel ArrayTechnology484-Pin PBGA (23 x 23, 1-mm Pitch)[ZER Suffix]

Description

AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN, EMAC, and USB OTG PHY that are well suited for industrial apllications. The processor can support other applications, including: Single-board computers Home and industrial automation Human machine Interface The device supports high-level operating systems (OSs), such as: The following subsystems are part of the device: AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package. This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05 Sitara processor. AM3517/05 is a high-performance ARM Cortex-A8 microprocessor with speeds up to 600 MHz. The device offers 3D graphics acceleration while also supporting numerous peripherals, including DDR2, CAN, EMAC, and USB OTG PHY that are well suited for industrial apllications. The processor can support other applications, including: Single-board computers Home and industrial automation Human machine Interface The device supports high-level operating systems (OSs), such as: The following subsystems are part of the device: AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package. This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05 Sitara processor.