CDCDB800 Series

8-output clock buffer for PCIe® Gen 1 to Gen 6

Catalog

8-output clock buffer for PCIe® Gen 1 to Gen 6

Part	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Package / Case	Mounting Type	Number of Circuits	Supplier Device Package	Output	Ratio - Input:Output	Frequency - Max [Max]	Input	Type	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments CDCDB800RSLT			48-VFQFN Exposed Pad	Surface Mount	1	48-VQFN (6x6)	HCSL	1:8	250 MHz	Clock HCSL	Clock Buffer	105 °C	-40 °C	3.6 V	3 V
Texas Instruments CDCDB800RSLR			48-VFQFN Exposed Pad	Surface Mount	1	48-VQFN (6x6)	HCSL	1:8	250 MHz	Clock HCSL	Clock Buffer	105 °C	-40 °C	3.6 V	3 V

Catalog

8-output clock buffer for PCIe® Gen 1 to Gen 6

Key Features

• 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations8 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 72 mA maximum6-mm × 6-mm, 48-pin VQFN package8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations8 hardware output enable (OE#) controlsAdditive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum)Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (maximum)Additive phase jitter after DB2000Q filter: 38 fs, RMS (maximum)Supports Common Clock (CC) and Individual Reference (IR) architecturesSpread spectrum-compatibleOutput-to-output skew: < 50 psInput-to-output delay: < 3 nsFail-safe inputProgrammable output slew rate control3.3-V core and IO supply voltagesHardware-controlled low power mode (PD#)Current consumption: 72 mA maximum6-mm × 6-mm, 48-pin VQFN package

Description

The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package. The CDCDB800 is a 8-output LP-HCSL, DB800ZL-compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-6, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus interface and eight output enable pins allow the configuration and control of all eight outputs individually. The CDCDB800 is a DB800ZL derivative buffer and meets or exceeds the system parameters in the DB800ZL specification. It also meets or exceeds the parameters in the DB2000Q specification. The CDCDB800 is packaged in a 6-mm × 6-mm, 48-pin VQFN package.