CD4030B Series

Quadruple 2-input 3-V to 18-V XOR (exclusive OR) gates

Catalog

Quadruple 2-input 3-V to 18-V XOR (exclusive OR) gates

Part	Logic Type	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Package / Case [x]	Package / Case	Package / Case [y]	Voltage - Supply [Max]	Voltage - Supply [Min]	Input Logic Level - High [Max]	Input Logic Level - High [Min]	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Number of Inputs	Supplier Device Package	Current - Quiescent (Max) [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Circuits	Max Propagation Delay @ V, Max CL	Package / Case [custom]	Package / Case [custom]
Texas Instruments CD4030BNSR	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.209 "	14-SOIC	5.3 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2	14-SO	1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BMG4	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.154 in	14-SOIC	3.9 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2		1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BNSRG4	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.209 "	14-SOIC	5.3 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2	14-SO	1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BPW	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount		14-TSSOP		18 V	3 V	11 V	3.5 V	1.5 V	4 V	2	14-TSSOP	1 çA	3.4 mA	3.4 mA	4	100 ns	0.173 "	4.4 mm
Texas Instruments CD4030BM96G4	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.154 in	14-SOIC	3.9 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2		1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BEG4	XOR (Exclusive OR)	-55 °C	125 °C	Through Hole	0.3 "	14-DIP	7.62 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2		1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BM	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.154 in	14-SOIC	3.9 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2		1 çA	3.4 mA	3.4 mA	4	100 ns
Texas Instruments CD4030BMT	XOR (Exclusive OR)	-55 °C	125 °C	Surface Mount	0.154 in	14-SOIC	3.9 mm	18 V	3 V	11 V	3.5 V	1.5 V	4 V	2		1 çA	3.4 mA	3.4 mA	4	100 ns

Catalog

Quadruple 2-input 3-V to 18-V XOR (exclusive OR) gates

Key Features

• Medium-speed operation—tPHL, tPLH= 65 ns (typ.) at VDD= 10 V, CL= 50 pF100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Even and odd-parity generators and checkersLogical comparatorsAdders/subtractorsGeneral logic functionsData sheet acquired from Harris SemiconductorMedium-speed operation—tPHL, tPLH= 65 ns (typ.) at VDD= 10 V, CL= 50 pF100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Applications:Even and odd-parity generators and checkersLogical comparatorsAdders/subtractorsGeneral logic functionsData sheet acquired from Harris Semiconductor

Description

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function. The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).