SN74HC163-Q1 Series

High Speed CMOS Logic 4-Bit Binary Counter with Synchronous Reset

Catalog

High Speed CMOS Logic 4-Bit Binary Counter with Synchronous Reset

Part	Supplier Device Package	Number of Elements	Trigger Type	Direction	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case	Timing	Logic Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Reset	Number of Bits per Element	Mounting Type	Count Rate	Package / Case [custom]	Package / Case [custom]	Package / Case [x]	Package / Case [y]
Texas Instruments SN74HC163NG4	16-PDIP	1	Positive Edge	Up	85 °C	-40 °C	0.3 in	16-DIP	7.62 mm	Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Through Hole	36 MHz
Texas Instruments SN74HC163DBR	16-SSOP	1	Positive Edge	Up	85 °C	-40 °C		16-SSOP		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	36 MHz	0.209 in	5.3 mm
Texas Instruments SN74HC163PWR	16-TSSOP	1	Positive Edge	Up	85 °C	-40 °C		16-TSSOP		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	36 MHz			0.173 in	4.4 mm
Texas Instruments SN74HC163DBRE4	16-SSOP	1	Positive Edge	Up	85 °C	-40 °C		16-SSOP		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	36 MHz	0.209 in	5.3 mm
Texas Instruments SN74HC163DRE4	16-SOIC	1	Positive Edge	Up	85 °C	-40 °C		16-SOIC		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	36 MHz			0.154 in	3.9 mm
Texas Instruments SN74HC163PWT	16-TSSOP	1	Positive Edge	Up	85 °C	-40 °C		16-TSSOP		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	36 MHz			0.173 in	4.4 mm
Texas Instruments CD74HC163M96	16-SOIC	1	Positive Edge	Up	125 °C	-55 °C		16-SOIC		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	24 MHz			0.154 in	3.9 mm
Texas Instruments SN74HC163N	16-PDIP	1	Positive Edge	Up	85 °C	-40 °C	0.3 in	16-DIP	7.62 mm	Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Through Hole	36 MHz
Texas Instruments CD74HC163MT	16-SOIC	1	Positive Edge	Up	125 °C	-55 °C		16-SOIC		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	24 MHz			0.154 in	3.9 mm
Texas Instruments CD74HC163M	16-SOIC	1	Positive Edge	Up	125 °C	-55 °C		16-SOIC		Synchronous	Binary Counter	2 V	6 V	Synchronous	4	Surface Mount	24 MHz			0.154 in	3.9 mm

Catalog

High Speed CMOS Logic 4-Bit Binary Counter with Synchronous Reset

Key Features

• ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset’HC163, ’HCT163 4-Bit Binary Counter, Synchronous ResetSynchronous Counting and LoadingTwo Count Enable Inputs for n-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHThe CD54HCT161 is obsolete and no longer is supplied.Data sheet acquired from Harris Semiconductor.’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset’HC163, ’HCT163 4-Bit Binary Counter, Synchronous ResetSynchronous Counting and LoadingTwo Count Enable Inputs for n-Bit CascadingLook-Ahead Carry for High-Speed CountingFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHThe CD54HCT161 is obsolete and no longer is supplied.Data sheet acquired from Harris Semiconductor.

Description

These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QAhigh). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the ’HC163 devices is synchronous. A low level at the clear (CLR\) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR\ to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QAhigh). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.