ADS61JB23 Series

12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

Catalog

12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

Part	Architecture	Ratio - S/H:ADC	Sampling Rate (Per Second)	Package / Case	Number of A/D Converters	Input Type	Reference Type	Data Interface	Configuration	Supplier Device Package	Mounting Type	Voltage - Supply, Digital [Min]	Voltage - Supply, Digital [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Voltage - Supply, Analog [Max]	Voltage - Supply, Analog [Min]	Number of Inputs	Number of Bits
Texas Instruments ADS61JB23IRHAR	Pipelined	1:1	80 M	40-VFQFN Exposed Pad	1	Differential	External Internal	JESD204A	S/H-ADC	40-VQFN (6x6)	Surface Mount	1.7 V	1.9 V	85 °C	-40 °C	1.9 V 3.6 V	1.7 V 3 V	1	12 bits
Texas Instruments ADS61JB23IRHAT	Pipelined	1:1	80 M	40-VFQFN Exposed Pad	1	Differential	External Internal	JESD204A	S/H-ADC	40-VQFN (6x6)	Surface Mount	1.7 V	1.9 V	85 °C	-40 °C	1.9 V 3.6 V	1.7 V 3 V	1	12 bits

Catalog

12-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

Key Features

• Output Interface:Single-Lane and Dual-Lane InterfacesMaximum Data Rate of 1.6 GbpsMeets JESD204A SpecificationCML Outputs with Current Programmable from 2 mA – 32 mAPower Dissipation:440 mW at 80 MSPS in Single Lane ModePower Scales Down with Clock RateInput Interface: Buffered Analog Inputs71.7 dBFS SNR at 70 MHz IFAnalog Input FSR: 2 VppExternal and Internal (trimmed) Reference Support1.8V Supply (Analog and digital), 3.3 V Supply for Input BufferProgrammable Digital Gain: 0dB – 6dBStraight Offset Binary or Twos Complement OutputPackage:6 mm × 6 mm QFN-40Output Interface:Single-Lane and Dual-Lane InterfacesMaximum Data Rate of 1.6 GbpsMeets JESD204A SpecificationCML Outputs with Current Programmable from 2 mA – 32 mAPower Dissipation:440 mW at 80 MSPS in Single Lane ModePower Scales Down with Clock RateInput Interface: Buffered Analog Inputs71.7 dBFS SNR at 70 MHz IFAnalog Input FSR: 2 VppExternal and Internal (trimmed) Reference Support1.8V Supply (Analog and digital), 3.3 V Supply for Input BufferProgrammable Digital Gain: 0dB – 6dBStraight Offset Binary or Twos Complement OutputPackage:6 mm × 6 mm QFN-40

Description

The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance. The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C). The ADS61JB23 is a high-performance, low-power, single channel analog-to-digital converter with an integrated JESD204A output interface. Available in a 6 mm × 6 mm QFN package, with both single-lane and dual-lane output modes, the ADS61JB23 offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per IEEE Std 802.3-2002 part3, Clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample/hold switches and higher and more consistent input impedance. The ADS61JB23 is specified over the industrial temperature range (–40°C to 85°C).