SN74LVTH16373-EP Series

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Catalog

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Part	Supplier Device Package	Independent Circuits	Logic Type	Output Type	Circuit [custom]	Circuit [custom]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Delay Time - Propagation	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Package / Case	Package / Case	Package / Case [custom]
Texas Instruments CLVTH16373IDGGREP	48-TSSOP	2	D-Type Transparent Latch	Tri-State	8	8	64 mA	32 mA	2.9 ns	85 °C	-40 °C	Surface Mount	2.7 V	3.6 V	48-TFSOP	0.24 in	6.1 mm
Texas Instruments V62/04712-01XE	48-TSSOP	2	D-Type Transparent Latch	Non-Inverted Tri-State	8	8	64 mA	32 mA	3 ns	85 °C	-40 °C	Surface Mount	2.7 V	3.6 V	48-TFSOP	0.24 in	6.1 mm
Texas Instruments CLVTH16373MGQLREP	56-BGA Microstar Junior (7x4.5)	2	D-Type Transparent Latch	Tri-State	8	8	64 mA	32 mA	2.9 ns	125 °C	-55 °C	Surface Mount	2.7 V	3.6 V	56-VFBGA

Catalog

Enhanced Product 3.3-V Abt 16-Bit Transparent D-Type Latches With 3-State Outputs

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources(DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState-of-the-Art Advanced BiCMOS Technology(ABT) Design for 3.3-V Operation and Low Static-Power DissipationSupports Mixed-Mode Signal Operation (5-V Inputand Output Voltages With 3.3-V VCC)Supports Unregulated Battery Operation Down to2.7 VTypical VOLP(Output Ground Bounce) < 0.8 Vat VCC= 3.3 V, TA= 25°CIoffand Power-Up Tri-State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need forExternal Pullup/Pulldown ResistorsDistributed VCCand GND Pins Minimize High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA PerJESD 17ESD Protection Exceeds JESD 224000-V Human Body Model (A114-A)200-V Machine Model (A115-A)Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources(DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)Member of the Texas Instruments Widebus™ FamilyState-of-the-Art Advanced BiCMOS Technology(ABT) Design for 3.3-V Operation and Low Static-Power DissipationSupports Mixed-Mode Signal Operation (5-V Inputand Output Voltages With 3.3-V VCC)Supports Unregulated Battery Operation Down to2.7 VTypical VOLP(Output Ground Bounce) < 0.8 Vat VCC= 3.3 V, TA= 25°CIoffand Power-Up Tri-State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need forExternal Pullup/Pulldown ResistorsDistributed VCCand GND Pins Minimize High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutLatch-Up Performance Exceeds 500 mA PerJESD 17ESD Protection Exceeds JESD 224000-V Human Body Model (A114-A)200-V Machine Model (A115-A)

Description

The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. The SN74LVTH16373 is a 16-bit transparent D-type latch with tri-state outputs designed for low-voltage (3.3 V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.