LMK04828-EP Series

Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Catalog

Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Part	Package / Case	Frequency - Max [Max]	Supplier Device Package	Output	Ratio - Input:Output	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Circuits	Mounting Type	Input	Divider/Multiplier	Supplied Contents	Contents	Function	Secondary Attributes	Primary Attributes
Texas Instruments LMK04828BISQE/NOPB	64-WFQFN Exposed Pad	3.08 GHz	64-WQFN (9x9)	HSDS LCPECL LVCMOS LVDS LVPECL	3:15	Jitter Cleaner	3.45 V	3.15 V	85 °C	-40 °C	1	Surface Mount	LVCMOS LVDS LVPECL	Yes/No
Texas Instruments LMK04828BISQX/NOPB	64-WFQFN Exposed Pad	3.08 GHz	64-WQFN (9x9)	HSDS LCPECL LVCMOS LVDS LVPECL	3:15	Jitter Cleaner	3.45 V	3.15 V	85 °C	-40 °C	1	Surface Mount	LVCMOS LVDS LVPECL	Yes/No
Texas Instruments LMK04828SNKDTEP	64-WFQFN Exposed Pad		64-WQFN (9x9)									Surface Mount
Texas Instruments LMK04828BEVM						Timing									Board(s)	Board(s)	Clock Conditioner	Integrated VCO	Jitter Cleaner

Catalog

Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Key Features

• EP FeaturesGold BondwiresTemperature Range: –55 to +105 °CLead Finish SnPbMaximum Distribution Frequency: 3.2 GHzJESD204B SupportUltra-Low RMS Jitter88-fs RMS Jitter (12 kHz to 20 MHz)91-fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks From PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.2 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2Up to 1 Buffered VCXO/Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableMulti-Mode: Dual PLL, Single PLL, and Clock DistributionDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog Delay3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)EP FeaturesGold BondwiresTemperature Range: –55 to +105 °CLead Finish SnPbMaximum Distribution Frequency: 3.2 GHzJESD204B SupportUltra-Low RMS Jitter88-fs RMS Jitter (12 kHz to 20 MHz)91-fs RMS Jitter (100 Hz to 20 MHz)–162.5 dBc/Hz Noise Floor at 245.76 MHzUp to 14 Differential Device Clocks From PLL2Up to 7 SYSREF ClocksMaximum Clock Output Frequency 3.2 GHzLVPECL, LVDS, HSDS, LCPECL Programmable Outputs From PLL2Up to 1 Buffered VCXO/Crystal Output From PLL1LVPECL, LVDS, 2xLVCMOS ProgrammableMulti-Mode: Dual PLL, Single PLL, and Clock DistributionDual Loop PLLatinum™ PLL ArchitecturePLL1Up to 3 Redundant Input ClocksAutomatic and Manual Switchover ModesHitless Switching and LOSIntegrated Low-Noise Crystal Oscillator CircuitHoldover Mode When Input Clocks are LostPLL2Normalized [1 Hz] PLL Noise Floor of–227 dBc/HzPhase Detector Rate up to 155 MHzOSCin Frequency-DoublerTwo Integrated Low-Noise VCOs50% Duty Cycle Output Divides, 1 to 32(Even and Odd)Precision Digital Delay, Dynamically Adjustable25-ps Step Analog Delay3.15-V to 3.45-V OperationPackage: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8 mm)

Description

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees. The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems. The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.