CD74HCT73 Series
High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset
Manufacturer: Texas Instruments
Catalog
High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset
Key Features
• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOHHysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH
