AM6548 Series

Quad Arm® Cortex®-A53 and dual Arm Cortex-R5F Sitara™ processor with gigabit PRU-ICSS, 3D graphics

Catalog

Quad Arm® Cortex®-A53 and dual Arm Cortex-R5F Sitara™ processor with gigabit PRU-ICSS, 3D graphics

Part	Security Features	Display & Interface Controllers	Voltage - I/O	RAM Controllers	Number of Cores/Bus Width [custom]	Number of Cores/Bus Width [custom]	Co-Processors/DSP	Core Processor	Ethernet	Ethernet	Speed	Speed	Graphics Acceleration	Package / Case	Operating Temperature [custom]	USB	Mounting Type	Additional Interfaces
Texas Instruments AM6548BACDXEAF	3DES AES DRBG MD5 PKA SHA	LVDS MIPI-CSI	1.2 V 1.35 V 1.8 V 3.3 V	DDR3 DDR4 LPDDR4	4 Core	32 Bit	GPU PowerVR SGX544-MP1 3D	ARM® Cortex®-A53 ARM® Cortex®-R5F	10 Mbps 100 Mbps 1000 Mbps	2	1.1 GHz	400 MHz		784-LFBGA FCBGA	-40 °C 105 °C	USB 2.0 (1) USB 3.1 (1)	Surface Mount	CAN I2C I2S McASP McSPI MMC/SD/SDIO QSPI TDM UART

Catalog

Quad Arm® Cortex®-A53 and dual Arm Cortex-R5F Sitara™ processor with gigabit PRU-ICSS, 3D graphics

Key Features

• Processor cores:Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHzUp to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDEDEach A53 core has 32KB L1 ICache and 32K L1 DCacheDual-core Arm Cortex-R5F at up to 400 MHzSupports lockstep mode16KB ICache, 16KB DCache, and 64KB RAM per R5F coreIndustrial subsystem:Three gigabit Industrial Communication Subsystems (PRU_ICSSG)Up to two 10/100/1000 Ethernet ports per PRU_ICSSGSupports two SGMII ports (2)Compatibility with 10/100Mb PRU-ICSS24× PWMs per PRU_ICSSGCycle-by-cycle controlEnhanced trip control18× Sigma-delta filters per PRU_ICSSGShort circuit logicOver-current logic6× Multi-protocol position encoder interfaces per PRU_ICSSGMemory subsystem:Up to 2MB of on-chip L3 RAM with SECDEDMulti-core Shared Memory Controller (MSMC)Up to 2MB (2 banks × 1MB) SRAM with SECDEDShared coherent Level 2 or Level 3 memory-mapped SRAMShared coherent Level 3 Cache256-bit processor port bus and 40-bit physical address busCoherent unified bi-directional interfaces to connect to processors or device mastersL2, L3 Cache pre-warming and post flushingBandwidth management with starvation boundOne infrastructure master interfaceSingle external memory master interfaceSupports distributed virtual systemSupports internal DMA engine – Data Routing Unit (DRU)ECC error protectionDDR Subsystem (DDRSS)Supports DDR4 memory types up to DDR-160032-bit data bus and 7-bit SECDED bus8 GB of total addressable spaceGeneral-Purpose Memory Controller (GPMC)Functional Safety:Functional Safety-Compliant[Industrial]Developed for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware Integrity up to SIL 2Safety-related certificationIEC 61508 certified by TÜV SÜDFunctional safety features:ECC or parity on calculation-critical memories and internal bus interconnectFirewalls to help provide Freedom From Interference (FFI)Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAMHardware error injection support for test-for-diagnosticsError Signaling Modules (ESM) for capture of functional safety related errorsVoltage, temperature, and clock monitoringWindowed and non-windowed watchdog timers in multiple clock domainsMCU islandIsolation of the dual-core Arm Cortex-R5F microprocessor subsystemSeparate voltage, clocks, resets, and dedicated peripheralsInternal MCSPI connection to the rest of SoCSecurity:Secure boot supportedHardware-enforced root-of-trustSupport to switch root-of-trust via backup keySupport for takeover protection, IP protection, and anti-roll back protectionCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128/192/256 bits key sizes3DES – 56/112/168 bits key sizesMD5, SHA1SHA2 – 224/256/384/512DRBG with true random number generatorPKA (public key accelerator) to assist in RSA/ECC processingDMA supportDebugging securitySecure software-controlled debug accessSecurity aware debuggingTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure DMA path and interconnectSecure watchdog/timer/IPCSecure storage supportOn-the-fly encryption and authentication support for OSPI interfaceNetworking security support for data (payload) encryption/authentication via packet based hardware cryptographic engineSecurity coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security softwareSoC services:Device Management Security Controller (DMSC)Centralized SoC system controllerManages system services including initial boot, security, functional safety and clock/reset/power managementPower management controller for active and low power modesCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsTracing and debugging capabilitySixteen 32-bit general-purpose timersTwo data movement and control Navigator Subsystems (NAVSS)Ring Accelerator (RA)Unified DMA (UDMA)Up to 2 Timer Managers (TM) (1024 timers each)Multimedia:Display subsystemTwo fully input-mapped overlay managers associated with two display outputsOne port MIPI DPI parallel interfaceOne port OLDIPowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)One Camera Serial Interface-2 (MIPI CSI-2)One port video capture: BT.656/1120 (no embedded sync)High-speed interfaces:One Gigabit Ethernet (CPSW) interface supportingRMII (10/100) or RGMII (10/100/1000)IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPAudio/video bridging (P802.1Qav/D6.0)Energy-efficient Ethernet (802.3az)Jumbo frames (2024 bytes)Clause 45 MDIO PHY managementTwo PCI-Express ( PCIe) revision 3.1 subsystems (2)Supports Gen2 (5.0GT/s) operationTwo independent 1-lane, or a single 2-lane portSupport for concurrent root-complex and end-point operationUSB 3.1 Dual-Role Device (DRD) subsystem (2)One enhanced SuperSpeed Gen1 portOne USB 2.0 portEach port independently configurable as USB host, USB peripheral, or USB DRDGeneral connectivity:6× Inter-Integrated Circuit ( I2C™) ports5× configurable UART/IrDA/CIR modulesTwo simultaneous flash interfaces configured asTwo OSPI flash interfacesor HyperBus™ and OSPI1 flash interface2× 12-bit Analog-to-Digital Converters (ADC)Up to 4 Msamples/sEight multiplexed analog inputs8× Multichannel Serial Peripheral Interfaces (MCSPI) controllersTwo with internal connectionsSix with external interfacesGeneral-Purpose I/O (GPIO) pinsControl interfaces:6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modulesOne Enhanced Capture (ECAP) module3× Enhanced Quadrature Encoder Pulse (EQEP) modulesAutomotive interfaces:2× Modular Controller Area Network (MCAN) modules with full CAN-FD supportAudio interfaces:3× Multichannel Audio Serial Port (MCASP) modulesMedia and data storage:2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfacesSimplified power management:Simplified power sequence with full support for dual voltage I/OIntegrated LDOs reduces power solution complexityIntegrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated Power On Reset (POR) generation reducing power solution complexityIntegrated voltage supervisor for functional safety monitoringIntegrated power supply glitch detector for detecting fast power supply transientsAnalog/system integration:Integrated USB VBUS detectionFail safe I/O for DDR RESETAll I/O pins drivers disabled during reset to avoid bus conflictsDefault I/O pulls disabled during reset to avoid system conflictsSupport dynamic I/O pinmux configuration changeSystem-on-Chip (SoC) architecture:Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces28-nm CMOS technology23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)Processor cores:Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHzUp to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDEDEach A53 core has 32KB L1 ICache and 32K L1 DCacheDual-core Arm Cortex-R5F at up to 400 MHzSupports lockstep mode16KB ICache, 16KB DCache, and 64KB RAM per R5F coreIndustrial subsystem:Three gigabit Industrial Communication Subsystems (PRU_ICSSG)Up to two 10/100/1000 Ethernet ports per PRU_ICSSGSupports two SGMII ports (2)Compatibility with 10/100Mb PRU-ICSS24× PWMs per PRU_ICSSGCycle-by-cycle controlEnhanced trip control18× Sigma-delta filters per PRU_ICSSGShort circuit logicOver-current logic6× Multi-protocol position encoder interfaces per PRU_ICSSGMemory subsystem:Up to 2MB of on-chip L3 RAM with SECDEDMulti-core Shared Memory Controller (MSMC)Up to 2MB (2 banks × 1MB) SRAM with SECDEDShared coherent Level 2 or Level 3 memory-mapped SRAMShared coherent Level 3 Cache256-bit processor port bus and 40-bit physical address busCoherent unified bi-directional interfaces to connect to processors or device mastersL2, L3 Cache pre-warming and post flushingBandwidth management with starvation boundOne infrastructure master interfaceSingle external memory master interfaceSupports distributed virtual systemSupports internal DMA engine – Data Routing Unit (DRU)ECC error protectionDDR Subsystem (DDRSS)Supports DDR4 memory types up to DDR-160032-bit data bus and 7-bit SECDED bus8 GB of total addressable spaceGeneral-Purpose Memory Controller (GPMC)Functional Safety:Functional Safety-Compliant[Industrial]Developed for functional safety applicationsDocumentation available to aid IEC 61508 functional safety system designSystematic capability up to SIL 3Hardware Integrity up to SIL 2Safety-related certificationIEC 61508 certified by TÜV SÜDFunctional safety features:ECC or parity on calculation-critical memories and internal bus interconnectFirewalls to help provide Freedom From Interference (FFI)Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAMHardware error injection support for test-for-diagnosticsError Signaling Modules (ESM) for capture of functional safety related errorsVoltage, temperature, and clock monitoringWindowed and non-windowed watchdog timers in multiple clock domainsMCU islandIsolation of the dual-core Arm Cortex-R5F microprocessor subsystemSeparate voltage, clocks, resets, and dedicated peripheralsInternal MCSPI connection to the rest of SoCSecurity:Secure boot supportedHardware-enforced root-of-trustSupport to switch root-of-trust via backup keySupport for takeover protection, IP protection, and anti-roll back protectionCryptographic acceleration supportedSession-aware cryptographic engine with ability to auto-switch key-material based on incoming data streamSupports cryptographic coresAES – 128/192/256 bits key sizes3DES – 56/112/168 bits key sizesMD5, SHA1SHA2 – 224/256/384/512DRBG with true random number generatorPKA (public key accelerator) to assist in RSA/ECC processingDMA supportDebugging securitySecure software-controlled debug accessSecurity aware debuggingTrusted Execution Environment (TEE) supportedArm TrustZone based TEEExtensive firewall support for isolationSecure DMA path and interconnectSecure watchdog/timer/IPCSecure storage supportOn-the-fly encryption and authentication support for OSPI interfaceNetworking security support for data (payload) encryption/authentication via packet based hardware cryptographic engineSecurity coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security softwareSoC services:Device Management Security Controller (DMSC)Centralized SoC system controllerManages system services including initial boot, security, functional safety and clock/reset/power managementPower management controller for active and low power modesCommunication with various processing units over message managerSimplified interface for optimizing unused peripheralsTracing and debugging capabilitySixteen 32-bit general-purpose timersTwo data movement and control Navigator Subsystems (NAVSS)Ring Accelerator (RA)Unified DMA (UDMA)Up to 2 Timer Managers (TM) (1024 timers each)Multimedia:Display subsystemTwo fully input-mapped overlay managers associated with two display outputsOne port MIPI DPI parallel interfaceOne port OLDIPowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)One Camera Serial Interface-2 (MIPI CSI-2)One port video capture: BT.656/1120 (no embedded sync)High-speed interfaces:One Gigabit Ethernet (CPSW) interface supportingRMII (10/100) or RGMII (10/100/1000)IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPAudio/video bridging (P802.1Qav/D6.0)Energy-efficient Ethernet (802.3az)Jumbo frames (2024 bytes)Clause 45 MDIO PHY managementTwo PCI-Express ( PCIe) revision 3.1 subsystems (2)Supports Gen2 (5.0GT/s) operationTwo independent 1-lane, or a single 2-lane portSupport for concurrent root-complex and end-point operationUSB 3.1 Dual-Role Device (DRD) subsystem (2)One enhanced SuperSpeed Gen1 portOne USB 2.0 portEach port independently configurable as USB host, USB peripheral, or USB DRDGeneral connectivity:6× Inter-Integrated Circuit ( I2C™) ports5× configurable UART/IrDA/CIR modulesTwo simultaneous flash interfaces configured asTwo OSPI flash interfacesor HyperBus™ and OSPI1 flash interface2× 12-bit Analog-to-Digital Converters (ADC)Up to 4 Msamples/sEight multiplexed analog inputs8× Multichannel Serial Peripheral Interfaces (MCSPI) controllersTwo with internal connectionsSix with external interfacesGeneral-Purpose I/O (GPIO) pinsControl interfaces:6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modulesOne Enhanced Capture (ECAP) module3× Enhanced Quadrature Encoder Pulse (EQEP) modulesAutomotive interfaces:2× Modular Controller Area Network (MCAN) modules with full CAN-FD supportAudio interfaces:3× Multichannel Audio Serial Port (MCASP) modulesMedia and data storage:2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfacesSimplified power management:Simplified power sequence with full support for dual voltage I/OIntegrated LDOs reduces power solution complexityIntegrated SDIO LDO for handling automatic voltage transition for SD interfaceIntegrated Power On Reset (POR) generation reducing power solution complexityIntegrated voltage supervisor for functional safety monitoringIntegrated power supply glitch detector for detecting fast power supply transientsAnalog/system integration:Integrated USB VBUS detectionFail safe I/O for DDR RESETAll I/O pins drivers disabled during reset to avoid bus conflictsDefault I/O pulls disabled during reset to avoid system conflictsSupport dynamic I/O pinmux configuration changeSystem-on-Chip (SoC) architecture:Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces28-nm CMOS technology23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

Description

AM654x and AM652xSitara™ processorsare Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products. The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508. The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC. Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity. TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems. AM654x and AM652xSitara™ processorsare Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products. The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508. The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC. Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity. TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.