
SCAN15MB200 Series
Dual 1.5-Gbps 2:1/1:2 LVDS mux/buffer with pre-emphasis and IEEE 1149.6
Manufacturer: Texas Instruments
Catalog
Dual 1.5-Gbps 2:1/1:2 LVDS mux/buffer with pre-emphasis and IEEE 1149.6
Key Features
• 1.5 Gbps Data Rate Per ChannelConfigurable Off/On Pre-emphasis Drives Lossy Backplanes and CablesLVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible OutputsLow Output Skew and JitterOn-chip 100Ω Input and Output TerminationIEEE 1149.1 and 1149.6 Compliant15 kV ESD Protection on LVDS Inputs/OutputsHot Plug ProtectionSingle 3.3V SupplyIndustrial -40 to +85°C Temperature Range48-Pin WQFN PackageAll trademarks are the property of their respective owners.1.5 Gbps Data Rate Per ChannelConfigurable Off/On Pre-emphasis Drives Lossy Backplanes and CablesLVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible OutputsLow Output Skew and JitterOn-chip 100Ω Input and Output TerminationIEEE 1149.1 and 1149.6 Compliant15 kV ESD Protection on LVDS Inputs/OutputsHot Plug ProtectionSingle 3.3V SupplyIndustrial -40 to +85°C Temperature Range48-Pin WQFN PackageAll trademarks are the property of their respective owners.
Description
AI
The SCAN15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to CML or LVPECL signals.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and high-speed differential PCB interconnects. The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range.
The SCAN15MB200 is a dual-port 2 to 1 multiplexer and 1 to 2 repeater/buffer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to CML or LVPECL signals.
Integrated IEEE 1149.1 (JTAG) and 1149.6 circuitry supports testability of both single-ended LVTTL/CMOS and high-speed differential PCB interconnects. The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range.