Catalog
62 V, 1.0 A Power MOSFET, Logic Level
Key Features
• Temperature Compensated Gate-to-Drain Clamp Limits Voltage Stress Applied to the Device and Protects the Load From Overvoltage
• Integrated ESD Diode Protection
• Controlled Switching Minimizes RFI
• Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors
Description
AI
These devices feature current limiting for short circ protection, an integral gate-to-source clamp for ESD protection and gate-to-drain clamp for over-voltage protection. No additional gate series resistance is required when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor recommended to avoid a floating gate condition.The internal gate-to-source and gate-to-drain clamps allow the devices to be applied without use of external transient suppression components. The gate-tosource clamp protects the MOSFET input from electrostatic gate voltage stresses up to 2.0 kV. The gate-to-drain clamp protects the MOSFET drain from drain avalanche stresses that occur with inductive loads. This unique design provides voltage clamping that is essentially independent of operating temperature.
