Catalog
Quad UART with 64-Byte FIFO
Key Features
• ST16C654/654D Pin Compatible With Additional EnhancementsSupport up to:24-MHz Crystal Input Clock (1.5 Mbps)48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation16-MHz Input Clock (1 Mbps) for 1.8-V Operation64-Byte Transmit FIFO64-Byte Receive FIFO With Error FlagsProgrammable and Selectable Transmit and Receive FIFO TriggerLevels for DMA and Interrupt GenerationProgrammable Receive FIFO Trigger Levels for Software/HardwareFlow ControlSoftware/Hardware Flow ControlProgrammable Xon/Xoff CharactersProgrammable Auto-RTSand Auto-CTSOptional Data Flow Resume by Xon Any CharacterRS-485 Mode SupportSupport 1.8-V, 2.5-V, 3.3-V, or 5-V SupplyCharacterized for Operation From –40°C to 85°C,Available in Commercial and Industrial Temperature GradesSoftware-Selectable Baud-Rate GeneratorPrescaler Provides Additional Divide-by-4 FunctionProgrammable Sleep ModeProgrammable Serial Interface Characteristics5-, 6-, 7-, or 8-Bit CharactersEven, Odd, or No Parity Bit Generation and Detection1-, 1.5-, or 2-Stop Bit GenerationFalse Start Bit DetectionComplete Status Reporting Capabilities in Both Normal and Sleep ModeLine Break Generation and DetectionInternal Test and Loopback CapabilitiesFully Prioritized Interrupt System ControlsModem Control Functions (CTS,RTS,DSR,DTR,RI, andCD)Infrared Data Association (IrDA) CapabilityST16C654/654D Pin Compatible With Additional EnhancementsSupport up to:24-MHz Crystal Input Clock (1.5 Mbps)48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation16-MHz Input Clock (1 Mbps) for 1.8-V Operation64-Byte Transmit FIFO64-Byte Receive FIFO With Error FlagsProgrammable and Selectable Transmit and Receive FIFO TriggerLevels for DMA and Interrupt GenerationProgrammable Receive FIFO Trigger Levels for Software/HardwareFlow ControlSoftware/Hardware Flow ControlProgrammable Xon/Xoff CharactersProgrammable Auto-RTSand Auto-CTSOptional Data Flow Resume by Xon Any CharacterRS-485 Mode SupportSupport 1.8-V, 2.5-V, 3.3-V, or 5-V SupplyCharacterized for Operation From –40°C to 85°C,Available in Commercial and Industrial Temperature GradesSoftware-Selectable Baud-Rate GeneratorPrescaler Provides Additional Divide-by-4 FunctionProgrammable Sleep ModeProgrammable Serial Interface Characteristics5-, 6-, 7-, or 8-Bit CharactersEven, Odd, or No Parity Bit Generation and Detection1-, 1.5-, or 2-Stop Bit GenerationFalse Start Bit DetectionComplete Status Reporting Capabilities in Both Normal and Sleep ModeLine Break Generation and DetectionInternal Test and Loopback CapabilitiesFully Prioritized Interrupt System ControlsModem Control Functions (CTS,RTS,DSR,DTR,RI, andCD)Infrared Data Association (IrDA) Capability
Description
AI
The ’754C is a quad universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that four such devices are incorporated into the ’754C. The ’754C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.
The ’754C is available in a 64-pin TQFP PM package.RXRDYandTXRDYfunctionality is not supported in the TL16C754CPM device.
The ’754C is a quad universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. It incorporates the functionality of four UARTs, each UART having its own register set and FIFOs. The four UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that four such devices are incorporated into the ’754C. The ’754C offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.
Each UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1-, 1.5-, or 2-stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and software flow control and hardware flow control capabilities.
The ’754C is available in a 64-pin TQFP PM package.RXRDYandTXRDYfunctionality is not supported in the TL16C754CPM device.
