CD4085B Series

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Catalog

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Part	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Number of Inputs	Package / Case [x]	Package / Case [y]	Package / Case	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Logic Type	Number of Circuits	Package / Case [custom]	Package / Case [custom]	Supplier Device Package
Texas Instruments CD4085BM	Single-Ended	-55 °C	125 °C	8 Input	0.154 in	3.9 mm	14-SOIC	Surface Mount	18 V	3 V	6.8 mA	6.8 mA	AND INVERT Gate OR	2
Texas Instruments CD4085BE	Single-Ended	-55 °C	125 °C	8 Input	0.3 "	7.62 mm	14-DIP	Through Hole	18 V	3 V	6.8 mA	6.8 mA	AND INVERT Gate OR	2
Texas Instruments CD4085BPW	Single-Ended	-55 °C	125 °C	8 Input			14-TSSOP	Surface Mount	18 V	3 V	6.8 mA	6.8 mA	AND INVERT Gate OR	2	0.173 "	4.4 mm	14-TSSOP
Texas Instruments CD4085BM96	Single-Ended	-55 °C	125 °C	8 Input	0.154 in	3.9 mm	14-SOIC	Surface Mount	18 V	3 V	6.8 mA	6.8 mA	AND INVERT Gate OR	2
Texas Instruments CD4085BMT	Single-Ended	-55 °C	125 °C	8 Input	0.154 in	3.9 mm	14-SOIC	Surface Mount	18 V	3 V	6.8 mA	6.8 mA	AND INVERT Gate OR	2

Catalog

CMOS Dual 2-Wide 2-Input AND-OR-INVERT Gate

Key Features

• Medium-speed operation - tPHL= 90 ns; tPLH= 125 ns (typ.) at 10 VIndividual inhibit controlsStandardized symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Medium-speed operation - tPHL= 90 ns; tPLH= 125 ns (typ.) at 10 VIndividual inhibit controlsStandardized symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CNoise margin (over full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Description

CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates. The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes). CD4085 contains a pair of AND-OR-INVERT gates, each consisting of two 2-input AND gates driving a 3-input NOR gate. Individual inhibit controls are provided for both A-O-I gates. The CD4085B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).