74LVX273 Series

Low Voltage Octal D-Type Flip-Flop

Catalog

Low Voltage Octal D-Type Flip-Flop

Part	Trigger Type	Max Propagation Delay @ V, Max CL	Output Type	Clock Frequency	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Current - Quiescent (Iq)	Number of Elements	Input Capacitance	Number of Bits per Element	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case [y]	Package / Case	Package / Case [x]	Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package	Package / Case [y]
ON Semiconductor 74LVX273MTCX	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	4.4 mm	20-TSSOP	0.173 in	D-Type	4 mA	4 mA	20-TSSOP
ON Semiconductor 74LVX273MTCX	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	4.4 mm	20-TSSOP	0.173 in	D-Type	4 mA	4 mA	20-TSSOP
ON Semiconductor 74LVX273MX	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	0.295 in	20-SOIC		D-Type	4 mA	4 mA	20-SOIC	7.5 mm
ON Semiconductor 74LVX273MTC	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	4.4 mm	20-TSSOP	0.173 in	D-Type	4 mA	4 mA	20-TSSOP
ON Semiconductor 74LVX273M	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	0.295 in	20-SOIC		D-Type	4 mA	4 mA	20-SOIC	7.5 mm
ON Semiconductor 74LVX273MTC	Positive Edge	14.5 ns	Non-Inverted	90 MHz	85 °C	-40 °C	Surface Mount	4 çA	1	4 pF	8	3.6 V	2 V	4.4 mm	20-TSSOP	0.173 in	D-Type	4 mA	4 mA	20-TSSOP

Catalog

Low Voltage Octal D-Type Flip-Flop

Key Features

• Input voltage translation from 5V to 3V

• Ideal for low power/low noise 3.3V applications

• Guaranteed simultaneous switching noise level and dynamic threshold performance

Description

The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.