LMK5C33414A Series

Three DPLL, three APLL, four-input and 14-output network synchronizer with JESD204B/C and BAW VCO

Catalog

Three DPLL, three APLL, four-input and 14-output network synchronizer with JESD204B/C and BAW VCO

Part	Operating Temperature [Max]	Operating Temperature [Min]	Frequency - Max [Max]	Ratio - Input:Output [custom]	PLL	Supplier Device Package	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Mounting Type	Input	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Circuits	Package / Case	Output	Divider/Multiplier
Texas Instruments LMK5C33414ARGCT	85 °C	-40 °C	1.25 GHz	4:14		64-VQFN (9x9)			Surface Mount	HCSL LVCMOS LVDS LVPECL	3.465 V	3.135 V	1	64-VFQFN Exposed Pad	CML HSDS LVCMOS LVDS LVPECL	Yes/No

Catalog

Three DPLL, three APLL, four-input and 14-output network synchronizer with JESD204B/C and BAW VCO

Key Features

• Ultra-low jitter BAW VCO based Wireless clocks40fs typical/ 57fs maximum RMS jitter at 491.52MHz50fs typical/ 62fs maximum RMS jitter at 245.76MHzThree high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)Programmable DPLL loop bandwidth from 1mHz to 4kHz< 1ppt DCO frequency adjustment step sizeFour differential or single-ended DPLL inputs1Hz (1PPS) to 800MHz input frequencyDigital holdover and hitless switching14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formatsUp to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N1Hz (1PPS) to 1250MHz output frequency with programmable swing and common modePCIe Gen 1 to 6 compliantI2C, 3-wire SPI, or 4-wire SPI–40°C to 85°C operating temperatureUltra-low jitter BAW VCO based Wireless clocks40fs typical/ 57fs maximum RMS jitter at 491.52MHz50fs typical/ 62fs maximum RMS jitter at 245.76MHzThree high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Loops (APLLs)Programmable DPLL loop bandwidth from 1mHz to 4kHz< 1ppt DCO frequency adjustment step sizeFour differential or single-ended DPLL inputs1Hz (1PPS) to 800MHz input frequencyDigital holdover and hitless switching14 differential outputs with programmable HSDS, AC-LVPECL, LVDS, and HSCL formatsUp to 18 total frequency outputs when configured with 6 LVCMOS frequency outputs on OUT[1:0]_P/N, GPIO1, and GPIO2 and 12 differential outputs on OUT[13:2]_P/N1Hz (1PPS) to 1250MHz output frequency with programmable swing and common modePCIe Gen 1 to 6 compliantI2C, 3-wire SPI, or 4-wire SPI–40°C to 85°C operating temperature

Description

The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications. The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use. APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain. Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs. The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options. The LMK5C33414A is a high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of wireless communications and infrastructure applications. The device integrates three DPLLs and three APLLs to provide hitless switching and jitter attenuation with programmable loop bandwidth (LBW) and one external loop filter capacitor, maximizing flexibility and ease of use. APLL3 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology. The BAW APLL can generate 491.52MHz output clocks with 40fs typical / 60fs maximum RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 and APLL1 (conventional LC VCOs) provide options for a second or third frequency and/or synchronization domain. Reference validation circuitry monitors the DPLL reference inputs and automatically performs a hitless switch when the inputs are detected or lost. Zero-Delay Mode (ZDM) provides control over the phase relationship between inputs and outputs. The device is fully programmable through I2C or SPI. The integrated EEPROM can be used to customize system start-up clocks. The device also features factory default ROM profiles as fallback options.