TDA4VE-Q1 Series
Automotive system-on-a-chip for autoparking and driver assist with AI, vision pre-processing and GPU
Manufacturer: Texas Instruments
Catalog
Automotive system-on-a-chip for autoparking and driver assist with AI, vision pre-processing and GPU
Key Features
• Processor cores:Two C7x floating point, vector DSP, up to 1.0GHz, 160GFLOPS, 512GOPSDeep-learning matrix multiply accelerator (MMA), up to 8TOPS (8b) at 1.0GHzVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDepth and Motion Processing Accelerators (DMPAC)Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per Cortex-A72 coreUp to Six Arm Cortex-R5F MCUs at up to 1.0GHz16K I-Cache, 16K D-Cache, 64K L2 TCMTwo Arm Cortex-R5F MCUs in isolated MCU subsystemFour (TDA4VE) or Two (TDA4AL/TDA4VL) Arm Cortex-R5F MCUs in general compute partitionGPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VE and TDA4VL)Custom-designed interconnect fabric supporting near max processing entitlementMemory subsystem:Up to 4MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineUp to Two External Memory Interface (EMIF) modules with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/sTwo (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17GB/s per EMIFGeneral-Purpose Memory Controller (GPMC)One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECCFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SIL-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-B/SIL-2 targeted for Main DomainHardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main DomainSafety-related certificationISO 26262 plannedDevice security (on select part numbers):Secure boot with secure runtime supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:One PCI-Express (PCIe) Gen3 controllersUp to four lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationOne USB 3.0 dual-role device (DRD) subsystemEnhanced SuperSpeed Gen1 PortSupports Type-C switchingIndependently configurable as USB host, USB peripheral, or USB DRDTwo CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per laneCSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per laneAutomotive interfaces:Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD supportDisplay subsystem:One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)One eDP 4L (TDA4VE/TDA4VL)One DPIAudio interfaces:Five Multichannel Audio Serial Port (MCASP) modulesVideo acceleration:TDA4VE: H.264/H.265 Encode/Decode (up to 480MP/s)TDA4AL: H.264/H.265 Encode only (up to 480MP/s)TDA4VL: H.264/H.265 Encode/Decode (up to 240MP/s)Ethernet:Two RMII/RGMII interfacesFlash memory interfaces:Embedded MultiMediaCard Interface ( eMMC™ 5.1)One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI or HyperBus™ or QSPI, andOne QSPISystem-on-Chip (SoC) architecture:16-nm FinFET technology23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)Companion Power Management ICs (PMIC):Functional Safety-Compliant support up to ASIL-D / SIL-3 targetedFlexible mapping to support different use casesProcessor cores:Two C7x floating point, vector DSP, up to 1.0GHz, 160GFLOPS, 512GOPSDeep-learning matrix multiply accelerator (MMA), up to 8TOPS (8b) at 1.0GHzVision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceleratorsDepth and Motion Processing Accelerators (DMPAC)Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2GHz1MB shared L2 cache per dual-core Cortex-A72 cluster32KB L1 DCache and 48KB L1 ICache per Cortex-A72 coreUp to Six Arm Cortex-R5F MCUs at up to 1.0GHz16K I-Cache, 16K D-Cache, 64K L2 TCMTwo Arm Cortex-R5F MCUs in isolated MCU subsystemFour (TDA4VE) or Two (TDA4AL/TDA4VL) Arm Cortex-R5F MCUs in general compute partitionGPU IMG BXS-4-64, 256kB Cache, up to 800MHz, 50GFLOPS, 4GTexels/s (TDA4VE and TDA4VL)Custom-designed interconnect fabric supporting near max processing entitlementMemory subsystem:Up to 4MB of on-chip L3 RAM with ECC and coherencyECC error protectionShared coherent cacheSupports internal DMA engineUp to Two External Memory Interface (EMIF) modules with ECCSupports LPDDR4 memory typesSupports speeds up to 4266MT/sTwo (TDA4VE) or One (TDA4AL/TDA4VL) 32-bit data bus with inline ECC up to 17GB/s per EMIFGeneral-Purpose Memory Controller (GPMC)One (TDA4AL/TDA4VL) or Two (TDA4VE) 512KB on-chip SRAM in MAIN domain, protected by ECCFunctional Safety:Functional Safety-Complianttargeted (on select part numbers)Developed for functional safety applicationsDocumentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targetedSystematic capability up to ASIL-D/SIL-3 targetedHardware integrity up to ASIL-D/SIL-3 targeted for MCU DomainHardware integrity up to ASIL-B/SIL-2 targeted for Main DomainHardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main DomainSafety-related certificationISO 26262 plannedDevice security (on select part numbers):Secure boot with secure runtime supportCustomer programmable root key, up to RSA-4K or ECC-512Embedded hardware security moduleCrypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DESHigh speed serial interfaces:One PCI-Express (PCIe) Gen3 controllersUp to four lanes per controllerGen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiationOne USB 3.0 dual-role device (DRD) subsystemEnhanced SuperSpeed Gen1 PortSupports Type-C switchingIndependently configurable as USB host, USB peripheral, or USB DRDTwo CSI2.0 4L Camera Serial interface RX (CSI-RX) plus two CSI2.0 4L TX (CSI-TX) with DPHYMIPI CSI 1.3 Compliant + MIPI-DPHY 1.2CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per laneCSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per laneAutomotive interfaces:Twenty Modular Controller Area Network (MCAN) modules with full CAN-FD supportDisplay subsystem:One (TDA4AL/TDA4VL) or Two (TDA4VE) DSI 4L TX (up to 2.5K)One eDP 4L (TDA4VE/TDA4VL)One DPIAudio interfaces:Five Multichannel Audio Serial Port (MCASP) modulesVideo acceleration:TDA4VE: H.264/H.265 Encode/Decode (up to 480MP/s)TDA4AL: H.264/H.265 Encode only (up to 480MP/s)TDA4VL: H.264/H.265 Encode/Decode (up to 240MP/s)Ethernet:Two RMII/RGMII interfacesFlash memory interfaces:Embedded MultiMediaCard Interface ( eMMC™ 5.1)One Secure Digital 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)Two simultaneous flash interfaces configured asOne OSPI or HyperBus™ or QSPI, andOne QSPISystem-on-Chip (SoC) architecture:16-nm FinFET technology23mm x 23mm, 0.8-mm pitch, 770-pin FCBGA (ALZ)Companion Power Management ICs (PMIC):Functional Safety-Compliant support up to ASIL-D / SIL-3 targetedFlexible mapping to support different use cases
Description
AI
The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview: The "C7x" next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.
General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.
The TDA4VE TDA4AL TDA4VL processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart Vision Camera applications and built on extensive market knowledge accumulated over a decade of TI’s leadership in the Vision processor market. The TDA4AL provides high performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced vision camera applications. Key cores include next generation DSP with scalar and vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors for general compute, an integrated next generation imaging subsystem (ISP), video codec, and isolated MCU island. All protected by automotive grade safety and security hardware accelerators.
Key Performance Cores Overview: The "C7x" next generation DSP combines TI’s industry leading DSP and EVE cores into a single higher performance core and adds floating-point vector calculation capabilities, enabling backward compatibility for legacy code while simplifying software programming. The new "MMA" deep learning accelerator enables performance up to 8 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C. The dedicated Vision hardware accelerators provide vision pre-processing with no impact on system performance.
General Compute Cores and Integration Overview: Separate dual core cluster configuration of Arm® Cortex®-A72 facilitates multi-OS applications with minimal need for a software hypervisor. Up to four Arm® Cortex®-R5F subsystems enable low-level, timing critical processing tasks to leave the Arm® Cortex®-A72 core’s unencumbered for applications. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite, support for higher bit depth, and features targeting analytics applications. Integrated diagnostics and safety features support operations up to ASIL-D levels while the integrated security features protect data against modern day attacks. CSI2.0 ports enable multi sensor inputs. To further the integration, the TDA4VE TDA4AL TDA4VL family also includes an MCU island eliminating the need for an external system microcontroller.
