74LVC1G00GV-Q100 Series

Single 2-input NAND gate

Manufacturer: Freescale Semiconductor - NXP

Catalog

Single 2-input NAND gate

Part	Supplier Device Package	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Operating Temperature [Max]	Operating Temperature [Min]	Max Propagation Delay @ V, Max CL	Input Logic Level - Low [Max]	Input Logic Level - Low [Min]	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Circuits	Number of Inputs	Qualification	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Mounting Type	Current - Quiescent (Max) [Max]	Logic Type	Grade
Freescale Semiconductor - NXP 74LVC1G00GV-Q100H	SC-74A	SC-74A SOT-753	5.5 V	1.65 V	125 °C	-40 °C	4 ns	0.8 V	0.7 V	32 mA	32 mA	1	2	AEC-Q100	1.7 V	2 V	Surface Mount	4 µA	NAND Gate	Automotive
Freescale Semiconductor - NXP 74LVC1G00GX,125	5-X2SON (0.80x0.80)	4-XFDFN Exposed Pad	5.5 V	1.65 V	125 °C	-40 °C	4 ns	0.8 V	0.7 V	32 mA	32 mA	1	2		1.7 V	2 V	Surface Mount	4 µA	NAND Gate
Freescale Semiconductor - NXP 74LVC1G00GW-Q100H	5-TSSOP	5-TSSOP SC-70-5 SOT-353	5.5 V	1.65 V	125 °C	-40 °C	4 ns	0.8 V	0.7 V	32 mA	32 mA	1	2	AEC-Q100	1.7 V	2 V	Surface Mount	4 µA	NAND Gate	Automotive
Freescale Semiconductor - NXP 74LVC1G00GF/S500,1

Catalog

Single 2-input NAND gate

Key Features

• Automotive product qualification in accordance with AEC-Q100 (Grade 1)

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

• Wide supply voltage range from 1.65 V to 5.5 V

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• IOFFcircuitry provides partial Power-down mode operation

• ±24 mA output drive (VCC= 3.0 V)

• Latch-up performance exceeds 250 mA

• Direct interface with TTL levels

• Complies with JEDEC standard:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

Description

The 74LVC1G00-Q100 is a single 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.