74VHC161284 Series

IEEE 161284 Transceiver

Catalog

IEEE 161284 Transceiver

Part	Supplier Device Package	Mounting Type	Number of Bits	Supply Voltage [Min]	Supply Voltage [Max]	Package / Case	Package / Case	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Package / Case [y]	Package / Case [y]
ON Semiconductor 74VHC161284MTD	48-TSSOP	Surface Mount	8	4.5 V	5.5 V	48-TFSOP	0.24 in	6.1 mm	85 °C	-40 °C	IEEE STD 1284 Translation Transceiver
ON Semiconductor 74VHC161284MEA	48-SSOP	Surface Mount	8	4.5 V	5.5 V	48-BSSOP			85 °C	-40 °C	IEEE STD 1284 Translation Transceiver	0.295 in	7.5 mm

Catalog

IEEE 161284 Transceiver

Key Features

• Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals

• Replaces the function of two (2) 74ACT1284 devices

• All inputs have hysteresis to provide noise margin

• B and Y output resistance optimized to drive external cable

• B and Y outputs in high impedance mode during power down

• Inputs and outputs on cable side have internal pull-up resistors

• Flow-through pin configuration allows easy interface between the Peripheral and Host

Description

The VHC161284 contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard and is intended to be used in Extended Capabilities Port mode (ECP). The pinout allows for easy connection from the Peripheral (A-side) to the Host (cable side). Outputs on the cable side can be configured to be either open drain or high drive (± 14 mA). The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs (except HLH) and outputs on the cable side contain internal pull-up resistors connected to the VCCsupply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard LOW-drive CMOS outputs. The DIR input controls data flow on the A1-A8/B1-B8transceiver pins.