Catalog
Sitara processor: dual-Arm Cortex-A15
Key Features
• ARM®Cortex®-A15 MPCore™ CorePacUp to Four ARM Cortex-A15 Processor Cores atup to 1.4-GHz4MB L2 Cache Memory Shared by all Cortex-A15 Processor CoresFull Implementation of ARMv7-A ArchitectureInstruction Set32KB L1 Instruction and Data Caches per CoreAMBA 4.0 AXI Coherency Extension (ACE)Master Port, Connected to MSMC (MulticoreShared Memory Controller) for Low LatencyAccess to SRAM and DDR3Multicore Shared Memory Controller (MSMC)2 MB SRAM Memory for ARM CorePacMemory Protection Unit for Both SRAM andDDR3_EMIFMulticore Navigator8k Multi-Purpose Hardware Queues with QueueManagerOne Packet-Based DMA Engine for Zero-Overhead TransfersNetwork CoprocessorPacket Accelerator Enables Support forTransport Plane IPsec, GTP-U, SCTP,PDCPL2 User Plane PDCP (RoHC, Air Ciphering)1 Gbps Wire Speed Throughput at 1.5MPackets Per SecondSecurity Accelerator Engine Enables Support forIPSec, SRTP, 3GPP and WiMAX AirInterface, and SSL/TLS SecurityECB, CBC, CTR, F8, A5/3, CCM, GCM,HMAC, CMAC, GMAC, AES, DES, 3DES,Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bitHash), MD5Up to 6.4 Gbps IPSec and 3 Gbps AirCipheringEthernet SubsystemEight SGMII Ports with Wire Rate SwitchingIEEE1588 v2 (with Annex D/E/F) Support8 Gbps Total Ingress/Egress Ethernet BWfrom CoreAudio/Video Bridging (802.1Qav/D6.0)QOS CapabilityDSCP Priority MappingPeripheralsTwo PCIe Gen2 Controllers with Support forTwo Lanes per ControllerSupports Up to 5 GBaudOne HyperLinkSupports Connections to Other KeyStone ArchitectureDevices Providing ResourceScalabilitySupports Up to 50 GBaud10-Gigabit Ethernet (10-GbE) Switch SubsystemTwo SGMII/XFI Ports with Wire RateSwitching and MACSEC SupportIEEE1588 v2 (with Annex D/E/F) SupportOne 72-Bit DDR3/DDR3L Interface with Speeds Upto 1600 MTPS in DDR3 ModeEMIF16 InterfaceTwo USB 2.0/3.0 ControllersUSIM InterfaceTwo UART InterfacesThree I2C Interfaces32 GPIO PinsThree SPI InterfacesOne TSIPSupport 1024 DS0sSupport 2 Lanes at 32.768/16.3848.192Mbps Per LaneSystem ResourcesThree On-Chip PLLsSmartReflex Automatic Voltage ScalingSemaphore ModuleTwelve 64-Bit TimersFive Enhanced Direct Memory Access (EDMA)ModulesCommercial Case Temperature:0°C to 85°CExtended Case Temperature:–40°C to 100°CARM®Cortex®-A15 MPCore™ CorePacUp to Four ARM Cortex-A15 Processor Cores atup to 1.4-GHz4MB L2 Cache Memory Shared by all Cortex-A15 Processor CoresFull Implementation of ARMv7-A ArchitectureInstruction Set32KB L1 Instruction and Data Caches per CoreAMBA 4.0 AXI Coherency Extension (ACE)Master Port, Connected to MSMC (MulticoreShared Memory Controller) for Low LatencyAccess to SRAM and DDR3Multicore Shared Memory Controller (MSMC)2 MB SRAM Memory for ARM CorePacMemory Protection Unit for Both SRAM andDDR3_EMIFMulticore Navigator8k Multi-Purpose Hardware Queues with QueueManagerOne Packet-Based DMA Engine for Zero-Overhead TransfersNetwork CoprocessorPacket Accelerator Enables Support forTransport Plane IPsec, GTP-U, SCTP,PDCPL2 User Plane PDCP (RoHC, Air Ciphering)1 Gbps Wire Speed Throughput at 1.5MPackets Per SecondSecurity Accelerator Engine Enables Support forIPSec, SRTP, 3GPP and WiMAX AirInterface, and SSL/TLS SecurityECB, CBC, CTR, F8, A5/3, CCM, GCM,HMAC, CMAC, GMAC, AES, DES, 3DES,Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bitHash), MD5Up to 6.4 Gbps IPSec and 3 Gbps AirCipheringEthernet SubsystemEight SGMII Ports with Wire Rate SwitchingIEEE1588 v2 (with Annex D/E/F) Support8 Gbps Total Ingress/Egress Ethernet BWfrom CoreAudio/Video Bridging (802.1Qav/D6.0)QOS CapabilityDSCP Priority MappingPeripheralsTwo PCIe Gen2 Controllers with Support forTwo Lanes per ControllerSupports Up to 5 GBaudOne HyperLinkSupports Connections to Other KeyStone ArchitectureDevices Providing ResourceScalabilitySupports Up to 50 GBaud10-Gigabit Ethernet (10-GbE) Switch SubsystemTwo SGMII/XFI Ports with Wire RateSwitching and MACSEC SupportIEEE1588 v2 (with Annex D/E/F) SupportOne 72-Bit DDR3/DDR3L Interface with Speeds Upto 1600 MTPS in DDR3 ModeEMIF16 InterfaceTwo USB 2.0/3.0 ControllersUSIM InterfaceTwo UART InterfacesThree I2C Interfaces32 GPIO PinsThree SPI InterfacesOne TSIPSupport 1024 DS0sSupport 2 Lanes at 32.768/16.3848.192Mbps Per LaneSystem ResourcesThree On-Chip PLLsSmartReflex Automatic Voltage ScalingSemaphore ModuleTwelve 64-Bit TimersFive Enhanced Direct Memory Access (EDMA)ModulesCommercial Case Temperature:0°C to 85°CExtended Case Temperature:–40°C to 100°C
Description
AI
The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.
TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.
The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.
TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.
The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.
The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
