NB3N4666C Series

Quad LVCMOS Differential Line Receiver Translator, 3.3 V

Catalog

Quad LVCMOS Differential Line Receiver Translator, 3.3 V

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Data Rate	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Type	Package / Case [x]	Package / Case	Package / Case [y]	Number of Drivers/Receivers [custom]	Number of Drivers/Receivers [custom]	Mounting Type
ON Semiconductor NB3N4666CDTR2G	2.97 V	3.63 V	400 Mbps	16-TSSOP	85 °C	-40 °C	Receiver	0.173 in	16-TSSOP	4.4 mm	0	4	Surface Mount

Quad LVCMOS Differential Line Receiver Translator, 3.3 V

• High Impedance Outputs When Disabled

• Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input Signal Levels

• Maximum Data Rate of 400 Mbps

• Maximum Clock Frequency of 200 MHz

• 25 ps Typical Channel−to−Channel Skew

• 3.3 ns Maximum Propagation Delay

• 3.3 V ±10% Power Supply

• Supports Open, Short, and Terminated Input Fail−safe

• −40°C to +85°C Ambient Operating Temperature

• 16−Pin TSSOP, 5.0 mm x 4.4 mm x 1.2 mm, Pb−Free