DRA726 Series

1.5 GHz Arm Cortex-A15 with Graphics & DSP for Infotainment & Cluster

Catalog

1.5 GHz Arm Cortex-A15 with Graphics & DSP for Infotainment & Cluster

Part	Ethernet	Ethernet	USB	RAM Controllers	Graphics Acceleration	Qualification	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Display & Interface Controllers	Mounting Type	Grade	Supplier Device Package	Security Features	Core Processor	Voltage - I/O	Speed	Co-Processors/DSP	SATA	Additional Interfaces	Number of Cores/Bus Width
Texas Instruments DRA726APGABCQ1	1Gbps	10/100/1000Mbps	USB 2.0 (2) USB 3.0 (1)	DDR3 DDR3L		AEC-Q100	760-BFBGA FCBGA	-40 °C	125 ¯C	HDMI LCD	Surface Mount	Automotive	760-FCBGA (23x23)	Cryptography Debug Security Device Identity Isolation Firewalls Secure Boot Secure Storage Software IP Protection	ARM® Cortex®-A15	1.35 V 1.5 V 1.8 V 3.3 V	750 MHz	ARM® Cortex®-M4 BB2D C66x GPU IVA	SATA	1-Wire® CANbus DMA I2C IrDA McASP MMC/SD/SDIO PCIe QSPI UART USB 3.0	1 Core 32 Bit

Catalog

1.5 GHz Arm Cortex-A15 with Graphics & DSP for Infotainment & Cluster

Key Features

• Architecture designed for infotainment applicationsVideo, image, and graphics processing supportFull-HD video (1920 × 1080p, 60 fps)Multiple video inputs and video outputs2D and 3D graphicsArm®Cortex®-A15 microprocessor subsystemC66x floating-point VLIW DSP coresFully object-code compatible with C67x and C64x+Up to thirty-two 16 × 16-bit fixed-point multiplies per cycleUp to 512KB of on-chip L3 RAMLevel 3 (L3) and level 4 (L4) interconnectsDDR3/DDR3L External Memory Interface (EMIF) moduleSupports up to DDR3-1333 (667 MHz)Up to 2GB across single chip selectDual Arm®Cortex®-M4 Image Processing Units (IPU)IVA-HD subsystemDisplay subsystemDisplay controller with DMA engine and up to three pipelinesHDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant2D-graphics accelerator (BB2D) subsystemVivante®GC320 coreVideo Processing Engine (VPE)Single-core PowerVR™ SGX544 3D GPUOne Video Input Port (VIP) moduleSupport for up to four multiplexed input portsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) controller2-Port Gigabit Ethernet switchUp to two external portsSixteen 32-bit general-purpose timers32-bit MPU watchdog timerSix high speed Inter-Integrated Circuit (I2C™) portsHDQ/1-Wire®interfaceTen configurable UART/IrDA/CIR modulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad Serial Peripheral Interface (QSPI)Media Local Bus subsystem (MLBSS)Real-Time Clock subsystem (RTCSS)SATA interfaceEight Multichannel Audio Serial Port (McASP) modulesSuperSpeed USB 3.0 dual-role deviceHigh Speed USB 2.0 dual-role deviceHigh Speed USB 2.0 on-the-goFour MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)PCI-Express®(PCIe®) revision 3.0 subsystems with two 5-Gbps lanesOne 2-lane Gen2-compliant portor two 1-lane Gen2-compliant portsDual Controller Area Network (DCAN) modulesCAN 2.0B ProtocolMIPI®Camera Serial Interface 2 (CSI-2)Up to 215 General-Purpose I/O (GPIO) pinsDevice security featuresHardware crypto accelerators and DMAFirewallsJTAG lockSecure keysSecure ROM and BootCustomer programmable keys (Silicon Revision 2.1)Power, reset, and clock managementOn-chip debug with CTools technology28-nm CMOS technology23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)Architecture designed for infotainment applicationsVideo, image, and graphics processing supportFull-HD video (1920 × 1080p, 60 fps)Multiple video inputs and video outputs2D and 3D graphicsArm®Cortex®-A15 microprocessor subsystemC66x floating-point VLIW DSP coresFully object-code compatible with C67x and C64x+Up to thirty-two 16 × 16-bit fixed-point multiplies per cycleUp to 512KB of on-chip L3 RAMLevel 3 (L3) and level 4 (L4) interconnectsDDR3/DDR3L External Memory Interface (EMIF) moduleSupports up to DDR3-1333 (667 MHz)Up to 2GB across single chip selectDual Arm®Cortex®-M4 Image Processing Units (IPU)IVA-HD subsystemDisplay subsystemDisplay controller with DMA engine and up to three pipelinesHDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant2D-graphics accelerator (BB2D) subsystemVivante®GC320 coreVideo Processing Engine (VPE)Single-core PowerVR™ SGX544 3D GPUOne Video Input Port (VIP) moduleSupport for up to four multiplexed input portsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) controller2-Port Gigabit Ethernet switchUp to two external portsSixteen 32-bit general-purpose timers32-bit MPU watchdog timerSix high speed Inter-Integrated Circuit (I2C™) portsHDQ/1-Wire®interfaceTen configurable UART/IrDA/CIR modulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad Serial Peripheral Interface (QSPI)Media Local Bus subsystem (MLBSS)Real-Time Clock subsystem (RTCSS)SATA interfaceEight Multichannel Audio Serial Port (McASP) modulesSuperSpeed USB 3.0 dual-role deviceHigh Speed USB 2.0 dual-role deviceHigh Speed USB 2.0 on-the-goFour MultiMedia Card/Secure Digital®/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)PCI-Express®(PCIe®) revision 3.0 subsystems with two 5-Gbps lanesOne 2-lane Gen2-compliant portor two 1-lane Gen2-compliant portsDual Controller Area Network (DCAN) modulesCAN 2.0B ProtocolMIPI®Camera Serial Interface 2 (CSI-2)Up to 215 General-Purpose I/O (GPIO) pinsDevice security featuresHardware crypto accelerators and DMAFirewallsJTAG lockSecure keysSecure ROM and BootCustomer programmable keys (Silicon Revision 2.1)Power, reset, and clock managementOn-chip debug with CTools technology28-nm CMOS technology23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)

Description

DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences. DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. Programmability is provided by a single-core Arm®Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm®processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard. DRA72x ("Jacinto™ 6 Eco") infotainment applications processors are developed on the same architecture as Jacinto 6 devices to meet the intense processing needs of the modern infotainment-enabled automobile experiences. DRA72x devices offer upward scalability to DRA74x devices, while being pin-compatible across the family, allowing Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 and Jacinto 6 Eco devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. Programmability is provided by a single-core Arm®Cortex®-A15 RISC CPU with Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm®processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm®, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment is available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA72x Jacinto 6 Eco processor family is qualified according to the AEC-Q100 standard.