Catalog
Dual Retriggerable Monostable Multivibrators
Key Features
• Inputs are TTL-voltage compatibleSchmitt-trigger circuitry on A , B, and CLR inputs for slow input transition ratesEdge triggered from active-high or active-low gated logic inputsRetriggerable for very long output pulsesOverriding clear terminates output pulseLatch-up performance exceeds 100mA per JESD 78, class IIInputs are TTL-voltage compatibleSchmitt-trigger circuitry on A , B, and CLR inputs for slow input transition ratesEdge triggered from active-high or active-low gated logic inputsRetriggerable for very long output pulsesOverriding clear terminates output pulseLatch-up performance exceeds 100mA per JESD 78, class II
Description
AI
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
