TSER4905 Series

4K DSI to V³Link™ serializer for high-resolution panels

Catalog

4K DSI to V³Link™ serializer for high-resolution panels

Part	Package / Case	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Function
Texas Instruments TSER4905RTDT	64-VFQFN Exposed Pad	64-VQFN (9x9)	85 °C	-20 C	Surface Mount Wettable Flank	Serializer
Texas Instruments TSER4905RTDR	64-VFQFN Exposed Pad	64-VQFN (9x9)	85 °C	-20 C	Surface Mount Wettable Flank	Serializer

Catalog

4K DSI to V³Link™ serializer for high-resolution panels

Key Features

• Single or dual port MIPI DSI receiverCompliant to D-PHY v1.2 and DSI v1.3.1Packed 16/18/24/30-bit RGB and 16-bit YCbCrLoosely packed 18-bit RGB and 20-bit 4:2:21 clock lane and 1-4 configurable data lanes per D-PHY PortUp to 2.5 Gbps/lane with skew calibrationSupports data lane swap and polarity inversionSupports both burst and non-burst modeSuperFrame Unpacking CapabilitySuitable for 4K @ 60 Hz video resolutionV 3Link Enhanced Video interfaceSupports 10.8/6.75/3.375 Gbps per channel; Up to 21.6 Gbps over dual channelsCoax/STP interconnect supportPort Splitting to enable Y-cable interfacesUltra-low latency control channelTwo I2C up to 1MHz (up to 3.4 MHz for local bus access)High speed GPIOsCompatibilityV 3Link Video and V 3Link Enhanced Video product familiesV 3Link Vision product familySecurity and diagnosticsVoltage and temperature monitoringLine Fault DetectionBIST and pattern generationCRC and error diagnosticsUnique ID for counterfeit protectionECC on control bitsAdvanced link robustness and EMC controlData scramblingSpread spectrum clocking generation (SSCG)Low power operation1.8-V and 1.1-V dual power supplyQualificationsISO 10605 and IEC 61000-4-2 ESD compliant64 pin QFN Wettable flanks 9 mm x 9 mmTemperature Range: −20℃ to +85℃Single or dual port MIPI DSI receiverCompliant to D-PHY v1.2 and DSI v1.3.1Packed 16/18/24/30-bit RGB and 16-bit YCbCrLoosely packed 18-bit RGB and 20-bit 4:2:21 clock lane and 1-4 configurable data lanes per D-PHY PortUp to 2.5 Gbps/lane with skew calibrationSupports data lane swap and polarity inversionSupports both burst and non-burst modeSuperFrame Unpacking CapabilitySuitable for 4K @ 60 Hz video resolutionV 3Link Enhanced Video interfaceSupports 10.8/6.75/3.375 Gbps per channel; Up to 21.6 Gbps over dual channelsCoax/STP interconnect supportPort Splitting to enable Y-cable interfacesUltra-low latency control channelTwo I2C up to 1MHz (up to 3.4 MHz for local bus access)High speed GPIOsCompatibilityV 3Link Video and V 3Link Enhanced Video product familiesV 3Link Vision product familySecurity and diagnosticsVoltage and temperature monitoringLine Fault DetectionBIST and pattern generationCRC and error diagnosticsUnique ID for counterfeit protectionECC on control bitsAdvanced link robustness and EMC controlData scramblingSpread spectrum clocking generation (SSCG)Low power operation1.8-V and 1.1-V dual power supplyQualificationsISO 10605 and IEC 61000-4-2 ESD compliant64 pin QFN Wettable flanks 9 mm x 9 mmTemperature Range: −20℃ to +85℃

Description

TSER4905 is a MIPI DSI to V 3Link bridge device. In conjunction with an V 3Link deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The TSER4905 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The V 3Link interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two V 3Link lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. This device can operate either in V 3Link Mode or V 3Link Enhanced Video Mode. In V 3Link Enhanced Video Mode, the device supports V 3Link Enhanced Video output over a single coax/STP cable operating up to 10.8 Gbps line rate or Dual Coax/STP cable operating up to 21.6 Gbps line rate, supporting 4K+ resolutions. In V 3Link mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link. In Vision compatible mode, the device is interoperable with V 3Link Vision deserializers supporting resolutions up to 8MP+/40fps. TSER4905 is a MIPI DSI to V 3Link bridge device. In conjunction with an V 3Link deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The TSER4905 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The V 3Link interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two V 3Link lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. This device can operate either in V 3Link Mode or V 3Link Enhanced Video Mode. In V 3Link Enhanced Video Mode, the device supports V 3Link Enhanced Video output over a single coax/STP cable operating up to 10.8 Gbps line rate or Dual Coax/STP cable operating up to 21.6 Gbps line rate, supporting 4K+ resolutions. In V 3Link mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link. In Vision compatible mode, the device is interoperable with V 3Link Vision deserializers supporting resolutions up to 8MP+/40fps.