AM263P4-Q1 Series

Automotive quad-core Arm® Cortex®-R5F MCU up to 400MHz with real-time control and expandable memory

Catalog

Automotive quad-core Arm® Cortex®-R5F MCU up to 400MHz with real-time control and expandable memory

Part	Core Processor	Program Memory Type	Number of I/O	Peripherals	Operating Temperature [Max]	Operating Temperature [Min]	Grade	Speed	Package / Case	Voltage - Supply (Vcc/Vdd) [Min]	Voltage - Supply (Vcc/Vdd) [Max]	Qualification	Supplier Device Package	Mounting Type	Oscillator Type	Program Memory Size	Core Size	RAM Size	Data Converters	Operating Temperature [custom]
Texas Instruments AM263P4ACOKFZCZRQ1	ARM® Cortex®-R4F	FLASH	139	AES DMA POR PWM SHA TRNG WDT	150 °C	-40 °C	Automotive	400 MHz	324-LFBGA	1.71 V 3.135 V	1.89 V 3.465 V	AEC-Q100	324-NFBGA (15x15)	Surface Mount	Internal	256 KB	32-Bit Quad-Core	3 M	A/D 6x12b SAR D/A 1x12b
Texas Instruments AM263P4ACOLFZCZR	ARM® Cortex®-R4F	FLASH	139	AES DMA POR PWM SHA TRNG WDT				400 MHz	324-LFBGA	1.71 V 3.135 V	1.89 V 3.465 V		324-NFBGA (15x15)	Surface Mount	Internal	256 KB	32-Bit Quad-Core	3 M	A/D 6x12b SAR D/A 1x12b	-40 °C 105 °C

Catalog

Automotive quad-core Arm® Cortex®-R5F MCU up to 400MHz with real-time control and expandable memory

Key Features

• Processor Cores:Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400MHz16KB I-cache with 64-bit ECC per CPU core16KB D-cache with 32-bit ECC per CPU corex256 integrated VIM per CPU Core256KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core clusterLockstep or Dual-core capable clustersTrigonometric Math Unit (TMU) for accelerating trigonometric functionsUp to 4x, one per R5F MCU coreMemory:1x Flash Subsystem with OptiFlash memory technology and eXecute In Place (XIP) support1x Octal Serial Peripheral Interface (OSPI), up to 133MHz SDR and DDRAM263P Flash-in-Package (ZCZ_F) variant includes 8MB OSPI Flash3MB of On-Chip RAM (OCSRAM)6 Banks x 512KBECC error protectionInternal DMA engine supportRemote L2 Cache for external memory, software programmable up to 128KB per CPU coreSystem on Chip (SoC) Services and Architecture:1x EDMA to support data movement functions2x Transfer Controllers (TPTC)1x Channel Controller (TPCC)Device Boot supported from the following interfaces:UART (Primary/Backup)QSPI NOR Flash (4S/1S) (Primary)OSPI NOR Flash (8S 50MHz SDR Mode0, 8S 25MHz DDR XSPI) (Primary)Interprocessor communication modulesSPINLOCK module for synchronizing processes running on multiple coresMAILBOX functionality implemented through CTRLMMR registersCentral Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routersTimer Modules:4x Windowed Watchdog Timer (WWDT)8x Real Time Interrupt (RTI) timerGeneral Connectivity:6x Universal Asynchronous RX-TX (UART)8x Serial Peripheral Interface (SPI) controllers5x Local Interconnect Network (LIN) ports4x Inter-Integrated Circuit (I2C) ports8x Modular Controller Area Network (MCAN) modules with CAN-FD support4x Fast Serial Interface Transmitters (FSITX)4x Fast Serial Interface Receivers (FSIRX)Up to 139 General-Purpose I/O (GPIO) pinsSensing & Actuation:Real-time Control Subsystem (CONTROLSS)Flexible Input/Output Crossbars (XBAR)5x 12-bit Analog-to-Digital Converters (ADC)6-input SAR ADC up to 4MSPS6x Single-ended channels OR3x Differential channelsHighly Configurable ADC Digital LogicXBAR Start of Conversion Triggers (SOC)User-defined Sample and Hold (S+H)Flexible Post-Processing Blocks (PPB)1x Resolver subsystem (ZCZ-S and ZCZ-F packages) with:2x Resolver to Digital Converter (RDC) OR2x 12-bit ADCs can also be used for general purpose4-input SAR ADC up to 3MSPS4x Single-ended channels OR2x Differential channels10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)1x 12-bit Digital-to-Analog Converter (DAC)32x Pulse Width Modulation (EPWM) modulesSingle or Dual PWM channelsAdvanced PWM ConfigurationsExtended HRPWM time resolution16x Enhanced Capture (ECAP) modules3x Enhanced Quadrature Encoder Pulse (EQEP) modules2x 4-Ch Sigma-Delta Filter Modules (SDFM)Additional Signal-multiplex Crossbars (XBAR)Industrial Connectivity:Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS)Dual core Programmable Real-Time Unit Subsystem (PRU0 / PRU1)Deterministic HardwareDynamic Firmware20-channel enhanced input (eGPI) per PRU20-channel enhanced output (eGPO) per PRUEmbedded Peripherals and Memory1x UART, 1x ECAP, 1x MDIO, 1x IEP1x 32KB Shared General Purpose RAM2x 8KB Shared Data RAM1x 16KB IRAM per PRUScratchPad (SPAD), MAC/CRCDigital encoder and sigma-delta control loopsThe PRU-ICSS enables advanced industrial protocols including:EtherCAT, Ethernet/IP™,PROFINET, IO-Link for orderDedicated Interrupt Controller (INTC)Dynamic CONTROLSS XBAR IntegrationHigh-Speed Interfaces:Integrated 3-port Gigabit Ethernet switch (CPSW) supporting up to two external portsMII (10/100), RMII (10/100), or RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY management512x ALE engine-based Packet ClassifiersPriority flow control with up to 2KB packet sizeFour CPU hardware interrupt pacingIP/UDP/TCP checksum offload in hardwareSecurity:Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITAArm Cortex-M4F based dedicated security controllerIsolated and secured RAMsPeripherals like Timers, WWDT, RTC, Interrupt ControllerSafety related peripherals like CRC, ESM, PBISTSecure boot supportDevice Take Over ProtectionHardware-enforced root-of-trust (RoT)Support for two sets of RoT keysAuthenticated boot supportEncrypted boot supportSW Anti-rollback protectionDebug securitySecure device debug only after cryptographic authenticationSupport for permanent debug/JTAG disableDevice ID and Key ManagementUnique ID (SoC ID)Support for OTP Memory (FUSEROM)Extensive Firewall SupportSystem Memory Protection Units (MPU) present at various interfacesCryptographic AccelerationCryptographic cores with DMA SupportAES - 128/192/256-bit key sizesSHA2 - 256/384/512-bit supportDeterministic random bit generator (DRBG) with pseudo and true random number generator (TRNG)Public Key Accelerator (PKA) to assist in RSA/Elliptic Curve Cryptography (ECC) processingFunctional Safety:Enables design of systems with functional safety requirementsError Signaling Module (ESM) with designated SAFETY_ERRORn pinECC or parity on calculation-critical memories4x Dual Clock Comparators (DCC)3x Self-Test Controller (STC)Programmable Built-In Self-Test (PBIST) and fault-injection for CPU and on-chip RAMRuntime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checksFunctional Safety-Complianttargeted [Industrial]Developed for functional safety applicationsDocumentation to be made available to aid IEC 61508 functional safety system designSystematic capability up to SIL-3 targetedHardware integrity up to SIL-3 targetedSafety-related certificationIEC 61508 plannedFunctional Safety-Complianttargeted [Automotive]Developed for functional safety applicationsDocumentation to be made available to aid ISO 26262 functional safety system designSystematic capability up to ASIL-D targetedHardware integrity up to ASIL-D targetedSafety-related certificationISO 26262 plannedData Storage1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interfaceOptimal Power Management SolutionRecommendedTPS653860-Q1Power Management ICs (PMIC)Companion PMIC specially designed to meet device power supply requirementsFlexible mapping and factory programmed configurations to support different use casesTechnology / Package:AEC-Q100 qualified for automotive applications45nm technologyZCZ PackageAM263x Compatible (ZCZ-C)Pin-to-Pin compatible option with AM263xAM263Px Resolver (ZCZ-S)Adds new Resolver Subsystem functionalityAM263Px Resolver with Flash-in-Package (ZCZ-F)Includes 1x internally connected Silicon in Package (SIP) 64Mb ISSI IS25LX064-LWLA3 OSPI Flash device; up to 133MHz SDR and DDR324-pin NFBGA15.0mm x 15.0mm0.8mm pitchProcessor Cores:Single, dual, and quad-core Arm Cortex-R5F MCU with each core running up to 400MHz16KB I-cache with 64-bit ECC per CPU core16KB D-cache with 32-bit ECC per CPU corex256 integrated VIM per CPU Core256KB Tightly-Coupled Memory (TCM) with 32-bit ECC per CPU core clusterLockstep or Dual-core capable clustersTrigonometric Math Unit (TMU) for accelerating trigonometric functionsUp to 4x, one per R5F MCU coreMemory:1x Flash Subsystem with OptiFlash memory technology and eXecute In Place (XIP) support1x Octal Serial Peripheral Interface (OSPI), up to 133MHz SDR and DDRAM263P Flash-in-Package (ZCZ_F) variant includes 8MB OSPI Flash3MB of On-Chip RAM (OCSRAM)6 Banks x 512KBECC error protectionInternal DMA engine supportRemote L2 Cache for external memory, software programmable up to 128KB per CPU coreSystem on Chip (SoC) Services and Architecture:1x EDMA to support data movement functions2x Transfer Controllers (TPTC)1x Channel Controller (TPCC)Device Boot supported from the following interfaces:UART (Primary/Backup)QSPI NOR Flash (4S/1S) (Primary)OSPI NOR Flash (8S 50MHz SDR Mode0, 8S 25MHz DDR XSPI) (Primary)Interprocessor communication modulesSPINLOCK module for synchronizing processes running on multiple coresMAILBOX functionality implemented through CTRLMMR registersCentral Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routersTimer Modules:4x Windowed Watchdog Timer (WWDT)8x Real Time Interrupt (RTI) timerGeneral Connectivity:6x Universal Asynchronous RX-TX (UART)8x Serial Peripheral Interface (SPI) controllers5x Local Interconnect Network (LIN) ports4x Inter-Integrated Circuit (I2C) ports8x Modular Controller Area Network (MCAN) modules with CAN-FD support4x Fast Serial Interface Transmitters (FSITX)4x Fast Serial Interface Receivers (FSIRX)Up to 139 General-Purpose I/O (GPIO) pinsSensing & Actuation:Real-time Control Subsystem (CONTROLSS)Flexible Input/Output Crossbars (XBAR)5x 12-bit Analog-to-Digital Converters (ADC)6-input SAR ADC up to 4MSPS6x Single-ended channels OR3x Differential channelsHighly Configurable ADC Digital LogicXBAR Start of Conversion Triggers (SOC)User-defined Sample and Hold (S+H)Flexible Post-Processing Blocks (PPB)1x Resolver subsystem (ZCZ-S and ZCZ-F packages) with:2x Resolver to Digital Converter (RDC) OR2x 12-bit ADCs can also be used for general purpose4-input SAR ADC up to 3MSPS4x Single-ended channels OR2x Differential channels10x Analog Comparators with Type-A programmable DAC reference (CMPSSA)10x Analog Comparators with Type-B programmable DAC reference (CMPSSB)1x 12-bit Digital-to-Analog Converter (DAC)32x Pulse Width Modulation (EPWM) modulesSingle or Dual PWM channelsAdvanced PWM ConfigurationsExtended HRPWM time resolution16x Enhanced Capture (ECAP) modules3x Enhanced Quadrature Encoder Pulse (EQEP) modules2x 4-Ch Sigma-Delta Filter Modules (SDFM)Additional Signal-multiplex Crossbars (XBAR)Industrial Connectivity:Programmable Real-Time Unit - Industrial Communication Subsystem (PRU-ICSS)Dual core Programmable Real-Time Unit Subsystem (PRU0 / PRU1)Deterministic HardwareDynamic Firmware20-channel enhanced input (eGPI) per PRU20-channel enhanced output (eGPO) per PRUEmbedded Peripherals and Memory1x UART, 1x ECAP, 1x MDIO, 1x IEP1x 32KB Shared General Purpose RAM2x 8KB Shared Data RAM1x 16KB IRAM per PRUScratchPad (SPAD), MAC/CRCDigital encoder and sigma-delta control loopsThe PRU-ICSS enables advanced industrial protocols including:EtherCAT, Ethernet/IP™,PROFINET, IO-Link for orderDedicated Interrupt Controller (INTC)Dynamic CONTROLSS XBAR IntegrationHigh-Speed Interfaces:Integrated 3-port Gigabit Ethernet switch (CPSW) supporting up to two external portsMII (10/100), RMII (10/100), or RGMII (10/100/1000)IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTPClause 45 MDIO PHY management512x ALE engine-based Packet ClassifiersPriority flow control with up to 2KB packet sizeFour CPU hardware interrupt pacingIP/UDP/TCP checksum offload in hardwareSecurity:Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITAArm Cortex-M4F based dedicated security controllerIsolated and secured RAMsPeripherals like Timers, WWDT, RTC, Interrupt ControllerSafety related peripherals like CRC, ESM, PBISTSecure boot supportDevice Take Over ProtectionHardware-enforced root-of-trust (RoT)Support for two sets of RoT keysAuthenticated boot supportEncrypted boot supportSW Anti-rollback protectionDebug securitySecure device debug only after cryptographic authenticationSupport for permanent debug/JTAG disableDevice ID and Key ManagementUnique ID (SoC ID)Support for OTP Memory (FUSEROM)Extensive Firewall SupportSystem Memory Protection Units (MPU) present at various interfacesCryptographic AccelerationCryptographic cores with DMA SupportAES - 128/192/256-bit key sizesSHA2 - 256/384/512-bit supportDeterministic random bit generator (DRBG) with pseudo and true random number generator (TRNG)Public Key Accelerator (PKA) to assist in RSA/Elliptic Curve Cryptography (ECC) processingFunctional Safety:Enables design of systems with functional safety requirementsError Signaling Module (ESM) with designated SAFETY_ERRORn pinECC or parity on calculation-critical memories4x Dual Clock Comparators (DCC)3x Self-Test Controller (STC)Programmable Built-In Self-Test (PBIST) and fault-injection for CPU and on-chip RAMRuntime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checksFunctional Safety-Complianttargeted [Industrial]Developed for functional safety applicationsDocumentation to be made available to aid IEC 61508 functional safety system designSystematic capability up to SIL-3 targetedHardware integrity up to SIL-3 targetedSafety-related certificationIEC 61508 plannedFunctional Safety-Complianttargeted [Automotive]Developed for functional safety applicationsDocumentation to be made available to aid ISO 26262 functional safety system designSystematic capability up to ASIL-D targetedHardware integrity up to ASIL-D targetedSafety-related certificationISO 26262 plannedData Storage1x 4-bit Multi-Media Card/Secure Digital (MMC/SD) interfaceOptimal Power Management SolutionRecommendedTPS653860-Q1Power Management ICs (PMIC)Companion PMIC specially designed to meet device power supply requirementsFlexible mapping and factory programmed configurations to support different use casesTechnology / Package:AEC-Q100 qualified for automotive applications45nm technologyZCZ PackageAM263x Compatible (ZCZ-C)Pin-to-Pin compatible option with AM263xAM263Px Resolver (ZCZ-S)Adds new Resolver Subsystem functionalityAM263Px Resolver with Flash-in-Package (ZCZ-F)Includes 1x internally connected Silicon in Package (SIP) 64Mb ISSI IS25LX064-LWLA3 OSPI Flash device; up to 133MHz SDR and DDR324-pin NFBGA15.0mm x 15.0mm0.8mm pitch

Description

The AM263Px Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263Px MCU family consists of multiple pin-to-pin compatible devices with up to four 400MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules. The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 3MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263Px devices. TI provides a complete set of microcontroller software and development tools for the AM263Px family of microcontrollers. The AM263Px Sitara™ Arm® Microcontrollers are built to meet the complex real-time processing needs of next generation industrial and automotive embedded products. The AM263Px MCU family consists of multiple pin-to-pin compatible devices with up to four 400MHz Arm® Cortex®-R5F cores. As an option, the Arm® R5F subsystem can be programmed to run in lockstep or dual-core mode for multiple functional safety configurations. The industrial communications subsystem (PRU-ICSS) enables integrated industrial Ethernet communication protocols such as PROFINET®, Ethernet/IP®, EtherCAT® (among many others), standard Ethernet connectivity, and even custom I/O interfaces. The family is designed for the future of motor control and digital power applications with advanced analog sensing and digital actuation modules. The multiple R5F cores are arranged in cluster subsystems with 256KB of shared tightly coupled memory (TCM) along with 3MB of shared SRAM, greatly reducing the need for external memory. Extensive ECC is included for on-chip memories, peripherals, and interconnects for enhanced reliability. Granular firewalls managed by the Hardware Security Manager (HSM) enable developers to implement stringent security-minded system design requirements. Cryptographic acceleration and secure boot are also available on AM263Px devices. TI provides a complete set of microcontroller software and development tools for the AM263Px family of microcontrollers.